 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NJU6854 132COMMON x 132RGB LCD DRIVER FOR 65,536-COLOR STN DISPLAY ! GENERAL DESCRIPTION The NJU6854 is a 132COMMON x 132RGB LCD driver for 65,536-color STN display. It contains common drivers, RGB drivers, a serial and a parallel MPU interface circuit, an internal LCD power supply, grayscale palettes and 278,784-bit display data RAM. The segment drivers for RGB (Red, Green, Blue) independently produce optimum 64 or 32 grayscales from a built-in grayscale palette, and the LSI achieves 65,536 colors (64x32x32). In addition, the NJU6854 operates with a low voltage of 1.7V and a low operating current, therefore it is ideally suited for battery-powered handheld applications. PACKAGE BUMP CHIP ! FEATURES # # # # # # # # # # # # # # # # # # 65,536-color STN LCD driver Built-in LCD Drivers : 132-common x 132RGB (396-segment drivers) Built-in Display Data RAM (DDRAM) : 278,784 bits for Graphic Display Programmable Display Mode - 64 grayscales(Green) - 32 grayscales(Red, Blue) 3 Areas Partial Display 8-/16-bit Parallel Interface Selectable 8-/16-bit Bus Length for Display Data Selectable 3-/4-line Serial Interface Selectable Programmable Duty Ratio and Bias Ratio Programmable Internal Voltage Booster : Maximum 6 times Programmable Contrast Control : 128-step Electronic Volume Register (EVR) Various Useful Instructions Low Operating Current Low Logic Voltage : 1.7V to 3.3V Wide LCD Voltage Range : 5.0V to 18.0V C-MOS Technology Slim Chip for COG Package : Bump Chip Ver.2004-06-29 -1- NJU6854 TABLE OF CONTENTS ! GENERAL DESCRIPTION PACKAGE........................................................................................... 1 ! FEATURES ................................................................................................................................................... 1 ! PAD LOCATION............................................................................................................................................ 4 ! PAD COORDINATES.................................................................................................................................... 6 ! BLOCK DIAGRAM ..................................................................................................................................... 12 ! LCD POWER SUPPLY BLOCK DIAGRAM ............................................................................................... 13 ! TERMINAL DESCRIPTION ........................................................................................................................ 14 ! FUNCTIONAL DESCRIPTION ................................................................................................................... 17 (1) MPU INTERFACE.................................................................................................................................... 17 (1-1) Selection of Parallel/Serial Interface Mode....................................................................................................................17 (1-2) Selection of MPU Mode.................................................................................................................................................17 (1-3) Data Recognition ...........................................................................................................................................................17 (1-4) Selection of 3-/4-line Serial Interface Mode...................................................................................................................17 (1-5) 4-line Serial Interface Mode...........................................................................................................................................17 (1-6) 3-line Serial Interface Mode...........................................................................................................................................18 (1-7) Data Write......................................................................................................................................................................19 (1-8) Data Read .....................................................................................................................................................................21 (1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) ..........................................................................................22 (2) INITIAL DISPLAY LINE............................................................................................................................ 22 (3) DDRAM.................................................................................................................................................... 23 (3-1) DDRAM Address Range................................................................................................................................................23 (3-2) Window Area for DDRAM Access..................................................................................................................................23 (3-3) DDRAM Access Direction..............................................................................................................................................24 (3-4) Segment Shift Direction.................................................................................................................................................26 (3-5) Block Diagram of DDRAM and Peripheral Circuit..........................................................................................................26 (3-6) DDRAM Mapping...........................................................................................................................................................27 (3-6-1) (REW, SWAP) = (0,0), SHIFT1 = "0", SHIFT0 = "0", VPC = "84H" (1/132 Duty), FVC = "00H", HCT = "00H", SSC1 and SSC2 = "0", EN3PTL = "0"................................................................................................................................27 (3-6-2) (REW, SWAP) = (0,0), SHIFT1 = "0", SHIFT0 = "0", VPC = "70H" (1/112 Duty), FVC = "00H", HCT = "0AH", SSC1 and SSC2 = "0", EN3PTL = "0"................................................................................................................................28 (3-7) The Relationship among Bit Assignment, X address and Segment Driver ....................................................................29 (4) PWM CONTROL...................................................................................................................................... 36 (5) FRAME RATE CONTROL(FRC) ............................................................................................................. 36 (6) DISPLAY TIMING GENERATOR............................................................................................................. 36 (7) DATA LATCH CIRCUIT............................................................................................................................ 36 (8) COMMON DRIVERS AND SEGMENT DRIVERS .................................................................................. 37 (9) OSCILLATOR........................................................................................................................................... 38 (10) LCD POWER SUPPLY ............................................................................................................................ 38 (10-1) Voltage Booster ...........................................................................................................................................................39 (10-2) Electrical Volume Register (EVR) ................................................................................................................................39 (10-3) Voltage Converter........................................................................................................................................................40 (10-3-1) Voltage Regulator .............................................................................................................................................40 (10-3-2) Reference Voltage Generator ...........................................................................................................................41 (10-3-3) LCD Bias Voltage Generator.............................................................................................................................41 (10-4) External Components for LCD Power Supply..............................................................................................................42 (10-5) Power ON/OFF............................................................................................................................................................45 (10-6) Discharge Circuit .........................................................................................................................................................45 (10-7) Reset Function ............................................................................................................................................................46 (11) INSTRUCTION TABLES.......................................................................................................................... 47 (12) INSTRUCTION DESCRIPTIONS ............................................................................................................ 51 (12-1) 8-bit Access Mode .......................................................................................................................................................51 (12-1-1) Instruction Register...........................................................................................................................................51 -2- Ver.2004-06-29 NJU6854 (12-1-2) Auto-increment of Instruction Register Address................................................................................................52 (12-2) 16-bit Access Mode .....................................................................................................................................................53 (12-2-1) Instruction Register...........................................................................................................................................53 (12-2-2) Auto Increment of Instruction Register Address................................................................................................53 (12-3) Oscillation Control .......................................................................................................................................................54 (12-4) Display Data Assignment/ Window Area ONOFF/Increment Control...........................................................................54 (12-5) Display Line Number ...................................................................................................................................................55 (12-6) Blank Line Number ......................................................................................................................................................55 (12-7) X Address ....................................................................................................................................................................56 (12-8) Y Address ....................................................................................................................................................................56 (12-9) Window End X Address ...............................................................................................................................................56 (12-10) Window End Y Address .............................................................................................................................................56 (12-11) Display Mode/Grayscale Mode ..................................................................................................................................56 (12-12) Oscillating Frequency Adjustment/Frequency Dividing..............................................................................................60 (12-13) Header COM .............................................................................................................................................................61 (12-14) Initial Display Line......................................................................................................................................................61 (12-15) Scan Start COM 1......................................................................................................................................................62 (12-16) Scan Start COM 2......................................................................................................................................................62 (12-17) Line Number of Partial Display 1 ...............................................................................................................................62 (12-18) Line Number of Partial Display 2 ...............................................................................................................................62 (12-19) N-Line Inversion ........................................................................................................................................................62 (12-20) Power Control 1.........................................................................................................................................................63 (12-21) Electronic Volume Control .........................................................................................................................................64 (12-22) Display Timing Signal Monitor/PBX Palette ...............................................................................................................64 (12-23) Power Control 2.........................................................................................................................................................65 (12-24) Booster Level/Amplifier Gain .....................................................................................................................................66 (12-25) Voltage Booster Clock ...............................................................................................................................................67 (12-26) Display Control ..........................................................................................................................................................68 (12-27) PWM Control .............................................................................................................................................................69 (12-28) Three Partial Display Areas/ LED Driver Control/REV Bit..........................................................................................70 (12-29) Discharge ON/OFF....................................................................................................................................................72 (12-30) LED Driver Data ........................................................................................................................................................72 (12-31) Instruction Table/Address ..........................................................................................................................................72 (12-32) Scan Start COM 3......................................................................................................................................................73 (12-33) Line Number of Partial Display 3 ...............................................................................................................................73 (12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31) ..........................................................................................74 (13) PARTIAL DISPLAY FUNCTION............................................................................................................... 89 (14) RELATIONSHIP BETWEEN LOGICAL COM NUMBER AND PHYSICAL COMMON DRIVER............. 90 (15) TYPICAL INSTRUCTION SEQUENCES ................................................................................................ 95 ! ABSOLUTE MAXIMUM RATINGS............................................................................................................. 98 ! RECOMMENDED OPERATING CONDITIONS ......................................................................................... 98 ! DC CHARACTERISTICS............................................................................................................................ 99 ! AC CHARACTERISTICS.......................................................................................................................... 101 (1) Write operation (80-type MPU) .............................................................................................................. 101 (2) Read operation (80-type MPU).............................................................................................................. 102 (3) Write operation (68-type MPU) .............................................................................................................. 103 (4) Read operation (68-type MPU).............................................................................................................. 104 (5) Serial interface ....................................................................................................................................... 105 (6) Display control timing............................................................................................................................. 106 (7) Reset input timing .................................................................................................................................. 107 ! INPUT/OUTPUT BLOCK DIAGRAM ....................................................................................................... 108 ! MPU CONNECTIONS............................................................................................................................... 110 Ver.2004-06-29 -3- NJU6854 ! PAD LOCATION COMB1 COMB0 DUMMY DUMMY SEGC131 SEGB131 SEGA131 SEGC130 SEGB130 SEGA130 DUMMY COMB25 COMB24 COMB23 SEGC67 SEGB67 SEGA67 SEGC66 SEGB66 SEGA66 DUMMY COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 DUMMY VSSH LDAT LSCK LREQ LRESB TEST SEL68 PS VDDA RESB CSB RS WRB RDB VDDA VSSA D0 D1 D2 D3 D4 D5 D6 D7 VDDA VSSA D8 D9 D10 D11 D12 D13 D14 D15 LP M FLM OSCO OSCI VSSL VSSL VDD VDD VEE DUMMY VSSH SEGA0~SEGC131, COMA0~COMA25, COMB0~COMB25, DUMMY 23 COMA26~COMA65, COMB26~COMB65, DUMMY 140 140 23 15 15 CPU interface pads and other pads 50 15 50 50 15 115 115 180 245 15, 40, 65, 115, 120 Bump Material : Au (gold) -4- Ver.2004-06-29 VREF VSSH VEE VBA VBA VREF NJU6854 CO M A23 CO M A24 CO M A25 DU M MY SEG C65 SEG B65 SEG A65 SEG C64 SEG B64 SEG A64 SEG C1 SEG B1 SEG A1 SEG C0 SEG B0 SEG A0 DU M MY DU M MY CO M A0 CO M A1 DUMMY COMA26 COMA27 COMA28 COMA29 COMA30 COMA31 COMA32 COMA59 COMA60 COMA61 COMA62 COMA63 COMA64 COMA65 DUMMY C 5N V0 V0 V1 V1 V2 V2 V3 V3 V4 VR EG VO U T VO U T C 1P V4 VSSH C 1P C 1N C 1N C 2P C 2P C 2N C 2N C 3P C 3P C 3N C 3N C 4P C 4P C 4N C 4N C 5P C 5P C 5N Note 1) The pads with the same name are connected within the chip. Note 2) Dummy pads are kept open.. UNIT: um ITEMS Chip size PAD pitch / space (bump) PAD open side PAD size (bump) BUMP height REMARK / PAD NO. With scribe lane (100 um) Driver pads pitch Interface pads Driver sides Interface sides Driver sides Interface sides All pads SIZE X 17,643 38 70~170 9 9 23 50 17.5 126 96 140 115 Y 2,180 ALIGN MARK DESIGN bump metal only 25 pattern forbidden area metal only bump 25 25 25 25 50 25 50 50 right bottom align mark 50 25 25 50 left bottom align mark Coordinates LEFT BOTTOM : X= -8157.92 Y= -515.62 RIGHT BOTTOM : X= 8157.92 Y= -515.62 Ver.2004-06-29 50 VSSH D UM M Y VSSH VR EG -5- NJU6854 ! PAD COORDINATES chip size 17,643x2,180 m ( chip center = 0:0 ) 2 PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad name DUMMY VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH LDAT LSCK LREQ LRESb TEST SEL68 PS VDDA RESb CSb RS WRb RDb VDDA VSSA D0 D1 D2 D3 D4 D5 D6 D7 VDDA VSSA D8 D9 D10 D11 D12 D13 D14 X(m) -8620.0 -8530.0 -8465.0 -8400.0 -8335.0 -8270.0 -8205.0 -8140.0 -8075.0 -8010.0 -7945.0 -7880.0 -7815.0 -7750.0 -7685.0 -7620.0 -7555.0 -7490.0 -7375.0 -7260.0 -7145.0 -7030.0 -6915.0 -6800.0 -6685.0 -6570.0 -6455.0 -6340.0 -6225.0 -6110.0 -5995.0 -5880.0 -5765.0 -5650.0 -5535.0 -5420.0 -5305.0 -5190.0 -5075.0 -4960.0 -4845.0 -4730.0 -4615.0 -4500.0 -4385.0 -4270.0 -4155.0 -4040.0 -3925.0 -3810.0 Y(m) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad name D15 LP M FLM OSCO OSCI VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VBA VBA VBA VBA VBA VREF VREF VREF VREF VREF VSSHA VSSHA VSSHA VSSHA VSSHA VSSHA X (m) -3695.0 -3580.0 -3465.0 -3350.0 -3235.0 -3120.0 -3005.0 -2940.0 -2875.0 -2810.0 -2745.0 -2680.0 -2615.0 -2525.0 -2460.0 -2395.0 -2330.0 -2265.0 -2200.0 -2110.0 -2045.0 -1980.0 -1915.0 -1850.0 -1785.0 -1720.0 -1655.0 -1590.0 -1525.0 -1460.0 -1395.0 -1330.0 -1265.0 -1200.0 -1110.0 -1045.0 -980.0 -915.0 -850.0 -760.0 -695.0 -630.0 -565.0 -500.0 -410.0 -345.0 -280.0 -215.0 -150.0 -85.0 Y (m) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pad name VSSHA VSSHA VSSHA VSSHA VREG VREG VREG VREG VREG VOUT VOUT VOUT VOUT VOUT VOUT C1+ C1+ C1+ C1+ C1+ C1+ C1C1C1C1C1C1C2+ C2+ C2+ C2+ C2+ C2+ C2C2C2C2C2C2C3+ C3+ C3+ C3+ C3+ C3+ C3C3C3C3C3- X (m) -20.0 45.0 110.0 175.0 340.0 405.0 470.0 535.0 600.0 690.0 755.0 820.0 885.0 950.0 1015.0 1105.0 1170.0 1235.0 1300.0 1365.0 1430.0 1520.0 1585.0 1650.0 1715.0 1780.0 1845.0 1935.0 2000.0 2065.0 2130.0 2195.0 2260.0 2350.0 2415.0 2480.0 2545.0 2610.0 2675.0 2765.0 2830.0 2895.0 2960.0 3025.0 3090.0 3180.0 3245.0 3310.0 3375.0 3440.0 Y (m) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -6- Ver.2004-06-29 NJU6854 chip size 17,643x2,180 m2 (chip center = 0:0 ) PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pad name C3C4+ C4+ C4+ C4+ C4+ C4+ C4C4C4C4C4C4C5+ C5+ C5+ C5+ C5+ C5+ C5C5C5C5C5C5V0 V0 V0 V0 V0 V0 V1 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V2 V3 V3 V3 V3 V3 V3 V4 X(m) 3505 3595 3660 3725 3790 3855 3920 4010 4075 4140 4205 4270 4335 4425 4490 4555 4620 4685 4750 4840 4905 4970 5035 5100 5165 5335 5400 5465 5530 5595 5660 5750 5815 5880 5945 6010 6075 6165 6230 6295 6360 6425 6490 6660 6725 6790 6855 6920 6985 7075 Y(m) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Pad name V4 V4 V4 V4 V4 VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH DUMMY DUMMY COMA65 COMA64 COMA63 COMA62 COMA61 COMA60 COMA59 COMA58 COMA57 COMA56 COMA55 COMA54 COMA53 COMA52 COMA51 COMA50 COMA49 COMA48 COMA47 COMA46 COMA45 COMA44 COMA43 COMA42 COMA41 COMA40 X (m) 7140 7205 7270 7335 7400 7490 7555 7620 7685 7750 7815 7880 7945 8010 8075 8140 8205 8270 8335 8400 8465 8530 8620 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 Y (m) -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -935.5 -794 -756 -718 -680 -642 -604 -566 -528 -490 -452 -414 -376 -338 -300 -262 -224 -186 -148 -110 -72 -34 4 42 80 118 156 194 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Pad name COMA39 COMA38 COMA37 COMA36 COMA35 COMA34 COMA33 COMA32 COMA31 COMA30 COMA29 COMA28 COMA27 COMA26 DUMMY DUMMY COMA25 COMA24 COMA23 COMA22 COMA21 COMA20 COMA19 COMA18 COMA17 COMA16 COMA15 COMA14 COMA13 COMA12 COMA11 COMA10 COMA9 COMA8 COMA7 COMA6 COMA5 COMA4 COMA3 COMA2 COMA1 COMA0 DUMMY DUMMY SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 X (m) 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8652 8607 8569 8531 8493 8455 8417 8379 8341 8303 8265 8227 8189 8151 8113 8075 8037 7999 7961 7923 7885 7847 7809 7771 7733 7695 7657 7619 7581 7543 7505 7467 7429 7391 7353 7315 Y (m) 232 270 308 346 384 422 460 498 536 574 612 650 688 726 764 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 Ver.2004-06-29 -7- NJU6854 chip size 17,643x2,180 m2 (chip center = 0:0 ) PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pad name SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 X(m) 7277 7239 7201 7163 7125 7087 7049 7011 6973 6935 6897 6859 6821 6783 6745 6707 6669 6631 6593 6555 6517 6479 6441 6403 6365 6327 6289 6251 6213 6175 6137 6099 6061 6023 5985 5947 5909 5871 5833 5795 5757 5719 5681 5643 5605 5567 5529 5491 5453 5415 Y(m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 PAD No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Pad name SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 X (m) 5377 5339 5301 5263 5225 5187 5149 5111 5073 5035 4997 4959 4921 4883 4845 4807 4769 4731 4693 4655 4617 4579 4541 4503 4465 4427 4389 4351 4313 4275 4237 4199 4161 4123 4085 4047 4009 3971 3933 3895 3857 3819 3781 3743 3705 3667 3629 3591 3553 3515 Y (m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 PAD No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 Pad name SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 X (m) 3477 3439 3401 3363 3325 3287 3249 3211 3173 3135 3097 3059 3021 2983 2945 2907 2869 2831 2793 2755 2717 2679 2641 2603 2565 2527 2489 2451 2413 2375 2337 2299 2261 2223 2185 2147 2109 2071 2033 1995 1957 1919 1881 1843 1805 1767 1729 1691 1653 1615 Y (m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 -8- Ver.2004-06-29 NJU6854 chip size 17,643x2,180 m2 (chip center = 0:0 ) PAD No. 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 Pad name SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 X(m) 1577 1539 1501 1463 1425 1387 1349 1311 1273 1235 1197 1159 1121 1083 1045 1007 969 931 893 855 817 779 741 703 665 627 589 551 513 475 437 399 361 323 285 247 209 171 133 95 57 19 -19 -57 -95 -133 -171 -209 -247 -285 Y(m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 PAD No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 Pad name SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 X (m) -323 -361 -399 -437 -475 -513 -551 -589 -627 -665 -703 -741 -779 -817 -855 -893 -931 -969 -1007 -1045 -1083 -1121 -1159 -1197 -1235 -1273 -1311 -1349 -1387 -1425 -1463 -1501 -1539 -1577 -1615 -1653 -1691 -1729 -1767 -1805 -1843 -1881 -1919 -1957 -1995 -2033 -2071 -2109 -2147 -2185 Y (m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 PAD No. 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 Pad name SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 X (m) -2223 -2261 -2299 -2337 -2375 -2413 -2451 -2489 -2527 -2565 -2603 -2641 -2679 -2717 -2755 -2793 -2831 -2869 -2907 -2945 -2983 -3021 -3059 -3097 -3135 -3173 -3211 -3249 -3287 -3325 -3363 -3401 -3439 -3477 -3515 -3553 -3591 -3629 -3667 -3705 -3743 -3781 -3819 -3857 -3895 -3933 -3971 -4009 -4047 -4085 Y (m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 Ver.2004-06-29 -9- NJU6854 chip size 17,643x2,180 m2 (chip center = 0:0 ) PAD No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 Pad name SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114 SEGB114 SEGC114 SEGA115 SEGB115 SEGC115 SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 X(m) -4123 -4161 -4199 -4237 -4275 -4313 -4351 -4389 -4427 -4465 -4503 -4541 -4579 -4617 -4655 -4693 -4731 -4769 -4807 -4845 -4883 -4921 -4959 -4997 -5035 -5073 -5111 -5149 -5187 -5225 -5263 -5301 -5339 -5377 -5415 -5453 -5491 -5529 -5567 -5605 -5643 -5681 -5719 -5757 -5795 -5833 -5871 -5909 -5947 -5985 Y(m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 PAD No. 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 Pad name SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 SEGA128 SEGB128 SEGC128 SEGA129 SEGB129 SEGC129 SEGA130 SEGB130 SEGC130 SEGA131 SEGB131 SEGC131 DUMMY DUMMY COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 X (m) -6023 -6061 -6099 -6137 -6175 -6213 -6251 -6289 -6327 -6365 -6403 -6441 -6479 -6517 -6555 -6593 -6631 -6669 -6707 -6745 -6783 -6821 -6859 -6897 -6935 -6973 -7011 -7049 -7087 -7125 -7163 -7201 -7239 -7277 -7315 -7353 -7391 -7429 -7467 -7505 -7543 -7581 -7619 -7657 -7695 -7733 -7771 -7809 -7847 -7885 Y (m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 PAD No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 Pad name COMB8 COMB9 COMB10 COMB11 COMB12 COMB13 COMB14 COMB15 COMB16 COMB17 COMB18 COMB19 COMB20 COMB21 COMB22 COMB23 COMB24 COMB25 DUMMY DUMMY COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB33 COMB34 COMB35 COMB36 COMB37 COMB38 COMB39 COMB40 COMB41 COMB42 COMB43 COMB44 COMB45 COMB46 COMB47 COMB48 COMB49 COMB50 COMB51 COMB52 COMB53 COMB54 COMB55 X (m) -7923 -7961 -7999 -8037 -8075 -8113 -8151 -8189 -8227 -8265 -8303 -8341 -8379 -8417 -8455 -8493 -8531 -8569 -8607 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 Y (m) 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 920.5 764 726 688 650 612 574 536 498 460 422 384 346 308 270 232 194 156 118 80 42 4 -34 -72 -110 -148 -186 -224 -262 -300 -338 -376 - 10 - Ver.2004-06-29 NJU6854 chip size 17,643x2,180 m2 (chip center = 0:0 ) PAD No. 751 752 753 754 755 756 757 758 759 760 761 Pad name COMB56 COMB57 COMB58 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 DUMMY X(m) -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 -8652 Y(m) -414 -452 -490 -528 -566 -604 -642 -680 -718 -756 -794 PAD No. Pad name X (m) Y (m) PAD No. Pad name X (m) Y (m) Ver.2004-06-29 - 11 - NJU6854 ! BLOCK DIAGRAM SEGA131 SEGB131 SEGC131 VEE VSS VSSHA V0 V1 V2 V3 V4 VOUT C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VREG VREF VBA LP FLM M OSCI OSCO TEST VDD VDDA VSSA VSS LCD Bias Voltage Generator Driver Power Segment Driver 396 Common Driver 132 Grayscale Palettes Y Address Register Y Address Decoder Y Address Counter Grayscale Control Circuit Data Latch Circuit Driver Control Line Address Decoder Line Address Register Ver.2004-06-29 Display Data RAM 132RGB x 132 278.784bit X address decoder Voltage Regulator Generator Display Timing Generator Oscillator Circuit RAM Interface X address counter X address register Data manager Display Control Duty Manager Instruction Decoder Register Control Register MPU Interface Bus I/O Buffer - 12 - SEL68 CSb RS WRb PS RESb RDb D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL LDAT LSCK LREQ LRESb Line Counter Voltage Booster COMA0 COMA65 COMB0 COMB65 Decoder Bus Holder SEGA0 SEGB0 SEGC0 NJU6854 ! LCD POWER SUPPLY BLOCK DIAGRAM Temp Coefficient Setting Register VBA + - VEE temperature bias circuit BG LCD Bias setting register VREG VREF + - + - + - V0 + This point is 1/2 VREG V1 + - V2 + VOUT C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VEE DC/DC booster Voltage converter step setting register VREG gain setting register Electric volume Register V3 + - V4 Note) When external VREF is used, keep Reference Voltage Circuit open (VGOFF="0", VBON="0"). Ver.2004-06-29 - 13 - NJU6854 ! TERMINAL DESCRIPTION Power Supply No. 64-69 26,32,42 33,43 57-63 95-104 206-222 Terminal VDD VDDA VSSA VSS VSSHA VSSH V0 V1 V2 V3 V4 C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VBA VEE VREF VREG VOUT I/O Power Power Power Power Power Power Description Power Supply for Logic Circuits VDDA is internally connected to VDD to fix SEL68 or P/S to "H" if necessary, and cannot be used as main power supply. * VDDA should be open if not used VSSA is internally connected to VSS to fix SEL68 or P/S to "L" if necessary, and cannot be used as main GND. * VSSA should be open if not used. GND for logic circuits GND for voltage converter circuits GND for voltage booster LCD Bias Voltages * When the internal LCD power supply is used, internal LCD bias voltages (V0-V4) are activated by the "Power Control" instruction. Stabilizing capacitors are required between each bias voltage and VSS. * When the external LCD power supply is used, LCD bias voltages are externally supplied on V0, V1, V2, V3 and V4 individually, with the following relation maintained: VSSH Power/O 116-127 128-139 140-151 152-163 164-175 85-89 70-84 90-94 105-109 110-115 Power Power Power Power Power Power Power Power Power Power - 14 - Ver.2004-06-29 NJU6854 MPU Interface No. 27 Terminal RESb D0/SCL D1/SDA D2 D3/SMODE D4/SPOL D5~D7 I/O I Reset * Active "L" Parallel Interface D7 to D0: 8-bit Bi-directional Bus(P/S="H") I/O Serial Interface SDA: Serial Data SCL: Shift Clock SMODE: 3-/4-line Serial Mode Select SPOL: RS Polarity Select (3-line Serial Interface Mode) 8-bit Bi-directional Bus * In the 16-bit bus length mode, D15-D8 are assigned to upper 8-bit data bus. * In the serial interface mode or the 8-bit parallel interface mode, D15-D8 should be fixed to "H" or "L". Chip Select * Active "L" Register Select * This signal interprets transferred data as display data or instruction. RS Data H Instruction L Display Data Description 34-41 44-51 28 D8~D15 CSb I/O I 29 RS I 31 RDb(E) I 30 WRb (R/W) I 80-series MPU Interface (P/S="H", SEL68="L") Data Read (RDb) Signal * Active "L" 68-series MPU Interface (P/S="H", SEL68="H") Enable Signal * Active "H" 80-series MPU Interface (P/S="H", SEL68="L") Data Write (WRb) Signal * Active "L" 68-series MPU Interface (P/S="H", SEL68="H") Data Read or Write (R/W) Signal R/W Status MPU Mode Select H Read L Write 24 SEL68 I SEL86 MPU H 68-series L 80-series Parallel/Serial Interface Mode Select Display / Read Data Serial Clock Instruction /Write H CSb RS D0 ~ D7 RDb, WRb L CSb RS SDA (D1) Write Only SCL (D0) In the serial interface mode (P/S="L"), RDb, WRb, D2 and D5-D15 should be fixed to "H" or "L",. P/S Chip Select Maker test terminal This terminal must be fixed to "H" in the user's application. 25 PS I 23 TEST I Ver.2004-06-29 - 15 - NJU6854 LCD Output No. Terminal I/O Segment Drivers Output REV Mode Normal Reverse SEGA0~ SEGA131, SEGB0~ SEGB131, SEGC0~ SEGC131 Turn-off 0 1 Turn-on 1 0 Description 295-690 O M signal Display RAM Data Nomal mode Reverse mode V2 V0 V0 V2 V3 VSS VSS V3 54 53 52 FLM M LP O O Normally open. Normally open. Normally open. Common Divers Output Data H L H L 225-292 COMA0~ COMA65 COMB0~ COMB65 O FR H H L L Output level VSSH V1 V0 V4 Oscillator 56 55 OSCI OSCO I O When using the internal resistor, connect OSCI to "L" and keep OSCO open When using an external resistor, connect OSCI and OSCO with the external resistor, and if using external clock, input 50% duty signal into the OSCI. White LED Driver Ports 19 20 21 22 LDAT LSCK LREQ LRESb I/O O O O White LED control port: data input/output White LED control port: shift clock output White LED control port: data request output White LED control port: reset output - 16 - Ver.2004-06-29 NJU6854 ! FUNCTIONAL DESCRIPTION (1) MPU INTERFACE (1-1) Selection of Parallel/Serial Interface Mode The P/S selects a parallel or a serial interface mode, as shown in Table 1. In the serial interface mode, neither display data in the DDRAM nor instruction data in the registers can be read out. Table 1 Selection of Parallel/Serial Interface Mode P/S I/F Mode CSb RS RDb WRb H Parallel I/F CSb RS RDb WRb L Serial I/F CSb RS NOTE) " -" : Fix to "H" or "L". (1-2) Selection of MPU Mode SEL68 SEL68 - SDA SDA SCL SCL Data D7-D0 (D15-D0) - In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 2. Table 2 Selection of MPU Mode SEL68 MPU Mode H 68-series MPU L 80-series MPU (1-3) Data Recognition CSb CSb CSb RS RS RS RDb E RDb WRb R/W WRb Data D7-D0 (D15-D0) D7-D0 (D15-D0) In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the combination of the RS, RDb and WRb (R/W) signals, as shown in Table 3. Table 3 RS H H L L Data Recognition (Parallel Interface Mode) 68-series 80-series R/W RDb WRb H L H L H L H L H L H L Function Read Instruction Write Instruction Read Display Data Write Display Data (1-4) Selection of 3-/4-line Serial Interface Mode In the serial interface mode, the SMODE selects 3- or 4-line serial interface mode, as shown in Table 4. Table 4 Selection of 3-/4-line Serial Interface Mode SMODE Serial Interface Mode H 3-line L 4-line (1-5) 4-line Serial Interface Mode While the chip select is active (CSb="L"), the SDA and SCL are enabled. While the chip select is inactive (CSb="H"), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized. 8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,..., and D0, and converted into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The data on the SDA is interpreted as display data or instruction according to the RS. Table 5 Data Recognition (4-line Serial Interface) RS Data Recognition H Instruction L Display Data Ver.2004-06-29 - 17 - NJU6854 Note that the SCL should be set to "L" right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb="H") temporary whenever 8-bit data transmission is completed. Fig 1 illustrates the interface timing of the 4-line serial interface mode. CSb RS SDA SCL 1 2 3 Fig 1 VALID D7 D6 D5 D4 D3 D2 D1 D0 4 5 6 7 8 4-line Serial Interface Timing (1-6) 3-line Serial Interface Mode While the chip select is active (CSb="L"), the SDA and SCL are enabled. While the chip select is not active (CSb="H"), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized. 9-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of RS, D7, D6,..., and D0, and then converted into 9-bit parallel data at the timing of the internal signal produced from the 9th SCL signal. The data on the SDA is interpreted as display data or instruction according to the combination of the RS bit and the SPOL status, as follows. Table 6 RS 0 1 Data Recognition (3-line Serial Interface) SPOL=L SPOL=H Data Recognition RS Data Recognition Display Data 0 Instruction Instruction 1 Display Data Note that the SCL should be set to "L" right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb="H") temporary whenever 9-bit data transmission is completed. Fig 2 illustrates the interface timing of the 3-line serial interface mode. CSb SDA SCL 1 2 3 Fig 2 RS D7 D6 D5 D4 D3 D2 D1 D0 4 5 6 7 8 9 3-line Serial Interface Timing - 18 - Ver.2004-06-29 NJU6854 (1-7) Data Write While the chip select is active (CSb="L"), the data from MPU can be written into the DDRAM or the instruction register. When the RS is "L", the data is interpreted as display data which is stored in the DDRAM. The display data is latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the 68-series MPU mode. Table 7 RS L H Data Recognition Data Recognition Display Data Instruction 8-bit access to DDRAM D0~D7 DATA0 DATA1 DATA2 DATA3 WRb RS Accessing to Instruction Register Accessing to DDRAM 8-bit access to Instruction Register MSB=0/Table Address /Register Address D0~D7 Data 1st Access WRb Datat0 MSB=1/Table Address /Counter Number Data 1st Access Datat0 Datatn-1 RS Fig 3 Data Write Operations in 8-bit Ver.2004-06-29 - 19 - NJU6854 16-bit access to DDRAM DATA0 DATA1 DATA2 DATA3 D8~D15 D0~D7 DATA0 DATA1 DATA2 DATA3 WRb RS Accessing to Instruction Register Accessing to DDRAM 16-bit access to Instruction Register MSB=0/Table MSB=0/Table Address/Register Address/Register Address Address MSB=1/Table Address/Counter Number(n) D8~D15 op code op code op code invalid DATA0 DATAn-2 D0~D7 WRb DATA0 DATA0 DATA1 DATAn-2 RS Fig 4 Data Write Operations in 16-bit - 20 - Ver.2004-06-29 NJU6854 (1-8) Data Read Just after address setting or data write operation, make sure to conduct dummy read operation once. The reason lies below, data from CPU is temporarily held in the built-in bus holder, and then released to the internal data bus, therefore a dummy data will be read out by the 1st "Display Data Read" instruction, the wanted data will be read out by the 2nd instruction. Display Data Read in 8-bit WRb D 0~ D 7 dummy read op code address set(AX,AY) address= n RDB RDb address= n address= n+1 RS Display Data Read in 16-bit WRb D 8~ D 15 dummy read op code dummy read n address set(AX,AY) address=n RDb data read address = n n+1 n+2 data read data read address = n+1 address = n+2 n n+1 n+2 D 0~ D 7 RS Instruction Data Read in 8-bit WRb D0~D7 Set " RA " 1D H instruction address Table address /register address data Data read RDb RS Instruction Data Read in 16-bit WRb Data read D 8 ~ D 15 1D H Set " RA " D 0~ D 7 / RDb instruction data invalid address 1 DH data invalid address Table address register address RS Fig 5 Data Read Operations Ver.2004-06-29 - 21 - NJU6854 (1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) Either 8- or 16-bit bus length can be selected by the D0 (SWIF) bit of the CFG register. SWIF = "0" : 8-bit bus D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z D8 D9 D10 D11 D12 D13 D14 D15 SWIF = "1" : 16-bit bus Bit assignment is determined by the D1 (UDS) bit of the CFG register. 16-bit access UDS = "0" Internal BUS IO PAD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D10 D11 D12 D13 D14 D15 D9 D10 D11 D12 D13 D14 D15 UDS = "1" Internal BUS IO PAD D8 D0 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D1 D2 D3 D4 D5 D6 D7 D9 D10 D11 D12 D13 D14 D15 8-bit access UDS = "0" Internal BUS IO PAD IO PAD 2 access nd D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D0 D0 D5 D5 D1 D1 D6 D6 D2 D2 D7 D7 D3 D3 D8 D0 D4 D4 D9 D1 D5 D5 D10 D2 D6 D6 D11 D3 D7 D7 D12 D4 D13 D14 D6 D15 D7 D5 st 1 access UDS = "1" Internal BUS IO PAD IO PAD D0 D0 D1 D1 D2 D2 st D3 D3 D4 D4 D0 D0 D5 D5 D1 D1 D6 D6 D2 D2 D7 D7 D3 D3 D8 D0 D4 D4 1 access D9 D10 D11 D12 D13 D14 D15 D1 D2 D3 D4 D5 D6 D7 D7 D5 D6 D5 D6 D7 2 access nd During 8-bit access, D15~D8 pins become high impedance, make sure fix them to H" or "L". (2) INITIAL DISPLAY LINE The Initial Display Line register(HST) specifies a DDRAM Y address, and display data corresponding to this address will be displayed by the Scan Start COM 1. The Y address specified by the Initial Display Line register is preset into the line counter whenever the FLM becomes "H". At the rising edge of the LP signal, the line counter is counted-up, then display data is latched into the data latch circuit. At the falling edge of the LP signal, the latch data is released to the grayscale control circuit to decide a grayscale level, then the segment drivers Ai, Bi and Ci (i=0 to 131) generate LCD waveforms. - 22 - Ver.2004-06-29 NJU6854 (3) DDRAM (3-1) DDRAM Address Range The DDRAM is capable of 132 bits for Y address and 2,112 bits (16-bit x 132-segment) for X address. The x and Y address are from 00H to 83 H. Address setting outside these ranges is not allowed, otherwise it may cause malfunctions. When auto-increment(auto-decrement) function is used during DDRAM access, Y address and/or X address will be automatically increased(decreased). This operation is independent from line counter count-up (count-down). X-address 83H 0H 16bit 16bit 0H Y-address 83H 16bit 16bit (3-2) Window Area for DDRAM Access Besides the normal DDRAM access discussed previously, it is possible to access only a specified window area by using CFG, ADRH, ADRL, EADRH and EADRL registers to define a start point and an end point. When auto-increment(auto-decrement) function enabled, Y address and/or X address will be automatically increased(decreased) whenever DDRAM is accessed. And, the start point is specified by the X address Register (ADRH) and Y address Register(ADRL), the end point by the Window End X address Register(EADRH) and Window End Y address Register(EADRL). For the details, refer to the Instruction Table. The typical sequence of the window area setting is listed below. 1. Set D7 (AIM1), D6 (AIM0), D5 (VWR), D4 (IDSY), D3 (IDSX), and D2 (WIN) bit of CFG register. 2. Set start point by ADRH and ADRL register. 3. Set end point by EADRH and EADRL register. 4. Window area is set up, and DDRAM can be accessed. X Address Start Point (X, Y) Y Address Window Area End Point (X, Y) DDRAM Area NOTE1) The following relationship should be maintained to avoid malfunctions. - AX (Window Start X address) < EX (Window End X address) < Maximum X address - AY (Window Start Y address) < EY (Window End Y address) < Maximum Y address Auto-increment in the window area Start Address End Address Start Address End Address NOTE2) Column Address Row Address NOTE3) When AIM[1:0]=(0,1), read-modify-write operation is valid. Ver.2004-06-29 - 23 - NJU6854 (3-3) DDRAM Access Direction Registers setting EADRH EADRL ADRH ADRL VWR IDSX IDSY WIN AIM DDDRAM Access Direction Remark 00,00 01,00 00 X 00 X 0 (H) (H) (H) (H) 00 0 0 0 00,83 00,00 83 X 00 X 0 (H) (H) (H) (H) 00 1 0 0 00,83 00,00 00 X 83 X 0 (H) (H) (H) (H) 00 0 1 0 00,83 01,83 00,00 83 X 83 X 0 (H) (H) (H) (H) 00 1 1 0 00,83 83,00 83,83 82,00 83,00 83,83 83,00 83,83 83,00 82,83 83,83 Window Area 06,10 07,10 06 7D 10 6A 1 (H) (H) (H) (H) 00 0 0 0 06,6A 7D,6A 7D,10 Window Area 06,10 7D 06 10 6A 1 (H) (H) (H) (H) 00 1 0 0 06,6A 7D,6A 7C,10 7D,10 Window Area 06,10 06 7D 6A 10 1 (H) (H) (H) (H) 00 0 1 0 06,6A 07,6A 7D,6A 7D,10 Window Area 06,10 7D 06 6A 10 1 (H) (H) (H) (H) 00 1 1 0 06,6A 7C,6A 7D,6A 7D,10 - 24 - Ver.2004-06-29 NJU6854 Registers setting EADRH EADRL ADRH ADRL VWR IDSX IDSY WIN AIM DDDRAM Access Direction Remark 00,00 00,01 00 X 00 X 0 (H) (H) (H) (H) 00 0 0 1 00,83 00,00 83 X 00 X 0 (H) (H) (H) (H) 00 1 0 1 00,83 00,00 00 X 83 X 0 (H) (H) (H) (H) 00 0 1 1 00,82 00,83 00,00 83 X 83 X 0 (H) (H) (H) (H) 00 1 1 1 00,83 83,00 83,83 83,00 83,01 83,83 83,00 83,83 83,00 83,82 83,83 Window Area 06 7D 10 6A 1 (H) (H) (H) (H) 00 0 0 1 06,10 06,11 06,6A 7D,10 7D,6A Window Area 06,10 7D 06 10 6A 1 (H) (H) (H) (H) 00 1 0 1 06,6A 7D,10 7D,11 7D,6A Window Area 06,10 06 7D 6A 10 1 (H) (H) (H) (H) 00 0 1 1 06.69 06,6A 7D,6A 7D,10 Window Area 06,10 7D 06 6A 10 1 (H) (H) (H) (H) 00 1 1 1 06,6A 7D,69 7D,6A 7D,10 Ver.2004-06-29 - 25 - NJU6854 (3-4) Segment Shift Direction The DDRAM access direction can be selected through setting the D7(REF) bit of the Display Control register (DISPLAY), This function enables to reverse segment shift direction to reduce the restriction on the IC location on an LCD module. (3-5) Block Diagram of DDRAM and Peripheral Circuit SEGMENT OUTPUT I/F Grayscale Control Circuit Internal Data Bus Data write Read data Data Latch REF,SWAP Segment data Y Address (00H~83H) Display Data RAM Y address X-Address (00H-83H) X Address Counter REF X Register MPU I/F Line Counter HST Register Ver.2004-06-29 Y Register - 26 - Y Counter NJU6854 (3-6) DDRAM Mapping (3-6-1) (REW, SWAP) = (0,0), SHIFT1 = "0", SHIFT0 = "0", VPC = "84H" (1/132 Duty), FVC = "00H", HCT = "00H", SSC1 and SSC2 = "0", EN3PTL = "0" HST=00H HST=05H COM output RAM Address D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEGA131 SEGB131 --------------------------------------SEGC0 -----------------------------------------------SEGC131 X=00H X address ------------------X=83H Y address COMA0 COMA1 COMA2 00H 01H 02H 03H 04H 05H 06H 07H --------------------------------------- --------------------------------------- COMA63 COMA64 COMA65 COMB0 COMB1 COMB2 COMB3 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H --------------------------------------- --------------------------------------- COMB63 COMB64 COMB65 81H 82H 83H Segment Output SEGA0 SEGB0 ---------- Ver.2004-06-29 --------------------------------------- --------------------------------------- - 27 - NJU6854 (3-6-2) (REW, SWAP) = (0,0), SHIFT1 = "0", SHIFT0 = "0", VPC = "70H" (1/112 Duty), FVC = "00H", HCT = "0AH", SSC1 and SSC2 = "0", EN3PTL = "0" HST=00H HST=05H COM output RAM Address D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEGA131 SEGB131 -----------------------------------------------------------------------SEGC0 SEGC131 X=00H X address ------------------X=83H Y address COMA0 COMA1 COMA2 COMA3 COMA4 COMA5 COMA6 COMA7 COMA8 COMA9 COMA10 COMA11 COMA12 --------------------------------------Unused COM driver 00H 01H 02H 03H 04H 05H 06H 07H ------------------------- COMA63 COMA64 COMA65 COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 COMB8 COMB9 COMB10 COMB11 COMB12 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Unused COM driver --------------------------------------- COMB63 COMB64 COMB65 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H Segment Output SEGA0 SEGB0 ---------- --------------------------------------- --------------------------------------- ------------------------- - 28 - Ver.2004-06-29 NJU6854 (3-7) The Relationship among Bit Assignment, X address and Segment Driver Three sub pixels(R, G, B) individually driven by 3 segment drivers (SEGAi, SEGBi, SEGCi) consist one pixel of the color STN panel. In the 65k display mode, 5-bit display data for SEGAi and SEGCi can output 32-level grayscale respectively, and 6-bit display data for SEGBi can output 64-level grayscale, so the total quantity of possible colors is 65,536(32x32x64). In 4k-color mode, 4-bit display data for every SEGAi, SEGBi and SEGCi, so the total quantity of possible colors is 4,096(16x16x16). Weighting value of display data is dependent on the status of the SWAP bit and the REF bit of DISPLAY register. 16-bit Bus Access (65k-color Mode) (REF,SWAP)=(0,0) or (1,1) MODED = 0 (65,536 color display) SEGCi SEGBi SEGAi i = 0 to 131 Palette Cj Palette Bj Palette Aj Grayscale Palette j = 0 to 31 Grayscale control PWMM[1:0]=00 for 64 level PWMM[1:0]=01 for 32 level PWMM[1:0]=11 for 128 level PWM control PWM control + 2 FRC PWM control D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Address : nH Note Internal Access X Address : nH (REF = 0) :83H - nH (REF = 1) (REF,SWAP)=(0,1) or (1,0) MODED = 0 (65,536 color display) SEGCi SEGBi SEGAi LSB Display data MPU Write Data MODE[1:0] = 00 i = 0 to 131 Palette Aj Palette Bj Palette Cj Grayscale Palette j = 0 to 31 Grayscale control PWMM[1:0]=00 for 64 level PWMM[1:0]=01 for 32 level PWMM[1:0]=11 for 128 level PWM control PWM control + 2 FRC PWM control D4 D3 D2 D1 D0 D10 D9 D8 D7 D6 D5 D15 D14 D13 D12 D11 Display data MSB LSB MPU Write Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Address : nH Note Internal Access X Address : nH (REF= 0) :83H - nH (REF= 1) Ver.2004-06-29 MODE[1:0] = 00 - 29 - NJU6854 16-bit Bus Access (4k-color Mode 1) (REF,SWAP)=(0,0) or (1,1) MODED = 1 (4,096 color display) SEGCi SEGBi SEGAi i = 0 to 131 Palette Cj Palette Bj Palette Aj Grayscale Palette j = 1, 3, 5 ... 29, 31 Grayscale control PWMM[1:0]=00 for 64 level PWMM[1:0]=01 for 32 level PWMM[1:0]=10 for 16 level PWMM[1:0]=11 for 128 level PWM control PWM control PWM control D15 D14 D13 D12 MSB D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 LSB Display data D10 D9 D8 D7 D4 D3 D2 D1 MPU Write Data MODE[1:0] = 01 X Address : nH Note Internal Access X Address : nH (REF = 0) :83H - nH (REF = 1) (REF,SWAP)=(0,1) or (1,0) MODED = 1 (4,096 color display) SEGCi SEGBi SEGAi i = 0 to 131 Palette Aj Palette Bj Palette Cj Grayscale Palette j = 1, 3, 5 ... 29, 31 Grayscale control PWMM[1:0]=00 for 64 level PWMM[1:0]=01 for 32 level PWMM[1:0]=10 for 16 level PWMM[1:0]=11 for 128 level PWM control PWM control PWM control D4 D3 D2 D1 MSB D15 D14 D13 D12 D10 D9 D8 D7 D15 D14 D13 D12 LSB Display data D10 D9 D8 D7 D4 D3 D2 D1 MPU Write Data MODE[1:0] = 01 X Address : nH Note Internal Access X Address : nH (REF = 0) :83H - nH (REF = 1) - 30 - Ver.2004-06-29 NJU6854 16-bit Bus Access (4k-color Mode 2) (REF,SWAP)=(0,0) or (1,1) MODED = 1 (4,096 color display) SEGCi SEGBi SEGAi i = 0 to 131 Palette Cj Palette Bj Palette Aj Grayscale Palette j = 1, 3, 5 ... 29, 31 Grayscale control PWMM[1:0]=00 for 64 level PWMM[1:0]=01 for 32 level PWMM[1:0]=10 for 16 level PWMM[1:0]=11 for 128 level PWM control PWM control PWM control D11 D10 D9 D8 MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Display data D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Address : nH Note Internal Access X Address : nH (REF = 0) :83H - nH (REF = 1) MPU Write Data MODE[1:0] = 10 (upper 4 bit invalid) (REF,SWAP)=(0,1) or (1,0) MODED = 1 (4,096 color display) SEGCi SEGBi SEGAi i = 0 to 131 Palette Aj Palette Bj Palette Cj Grayscale Palette j = 1, 3, 5 ... 29, 31 Grayscale control PWMM[1:0]=00 for 64 level PWMM[1:0]=01 for 32 level PWMM[1:0]=10 for 16 level PWMM[1:0]=11 for 128 level PWM control PWM control PWM control D3 D2 D1 D0 MSB D7 D6 D5 D4 D11 D10 D9 D8 LSB Display data D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Address : nH Note Internal Access X Address : nH (REF = 0) :83H - nH (REF = 1) MPU Write Data MODE[1:0] = 10 upper 4 bit invalid Ver.2004-06-29 - 31 - NJU6854 Relationship among Display Data, X address and Segment Drivers(16-bit Access Mode) 65k-color mode, MODE[1:0]=0H REF 0 1 UDS SWAP 0 1 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D8 D0 D9 D1 D10 D2 D11 D3 D12 D4 D13 D5 D14 D6 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D2 D10 D4 D12 D5 D13 D6 D14 D7 D15 D3 D11 D15 D7 D0 D8 D1 D9 X = 83H X = 00H D2 D10 D4 D12 D5 D13 D10 D2 D6 D14 D11 D3 D10 D2 D11 D3 D12 D4 D13 D5 D14 D6 D15 D7 D7 D15 D12 D4 D3 D11 D8 D0 D8 D0 D9 D1 D0 D8 D1 D9 : Palette C SEGC0 : : : Palette A SEGA0 Palette B SEGB0 Palette A SEGA131 Palette B SEGB131 Palette C SEGC131 REF 0 1 UDS SWAP 1 0 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D4 D12 D5 D13 D6 D14 D7 D15 D3 D11 D13 D5 D14 D6 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D2 D10 D15 D7 D0 D8 D1 D9 D8 D0 D9 D1 D10 D2 D11 D3 D12 D4 X = 83H X = 00H D4 D12 D5 D13 D6 D14 D7 D15 D13 D5 D14 D6 D15 D7 D2 D10 D3 D11 D0 D8 D1 D9 D9 D1 : : : : Palette C SEGA131 : : Palette C SEGA0 Palette B SEGB0 Palette A SEGC0 Palette B SEGB131 Palette A SEGC131 4k-color mode 1, MODE[1:0]=1H REF 0 1 UDS SWAP 0 1 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D9 D1 D10 D2 D11 D3 D12 D4 D15 D7 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D2 D10 D4 D12 D5 D13 D6 D14 D7 D15 D0 D8 D1 D9 X = 83H X = 00H D2 D10 D4 D12 D5 D13 D10 D2 D6 D14 D11 D3 D10 D2 D11 D3 D12 D4 D15 D7 D7 D15 D12 D4 D9 D1 D0 D8 D1 D9 : Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 : : : Palette A SEGA131 : : Palette B SEGB131 Palette C SEGC131 REF 0 1 UDS SWAP 1 0 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D4 D12 D5 D13 D6 D14 D7 D15 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D2 D10 D15 D7 D0 D8 D1 D9 D9 D1 D10 D2 D11 D3 D12 D4 X = 83H X = 00H D4 D12 D5 D13 D6 D14 D7 D15 D15 D7 D2 D10 D0 D8 D1 D9 D9 D1 : Palette A SEGC0 : : : Palette C SEGA131 0 1 Palette C SEGA0 Palette B SEGB0 : : Palette B SEGB131 Palette A SEGC131 : : - 32 - Ver.2004-06-29 NJU6854 4k-color mode, MODE[1:0]=2H REF 0 1 UDS SWAP 0 1 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D8 D0 D9 D1 D10 D2 D11 D3 D12 D4 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D2 D10 D3 D11 D13 D5 D14 D6 D15 D7 D0 D8 D1 D9 X = 83H X = 00H D2 D10 D10 D2 D10 D2 D11 D3 D12 D4 D13 D5 D14 D6 D15 D7 D3 D11 D11 D3 D8 D0 D9 D1 D0 D8 D8 D0 D1 D9 D9 D1 : Palette C SEGC0 : : : Palette A SEGA131 Palette A SEGA0 Palette B SEGB0 Palette B SEGB131 Palette C SEGC131 REF 0 1 UDS SWAP 1 0 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D2 D10 D3 D11 D0 D8 D1 D9 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D12 D4 D13 D5 D14 D6 D15 D7 D8 D0 D9 D1 D10 D2 D11 D3 X = 83H X = 00H D2 D10 D3 D11 D0 D8 D1 D9 D12 D4 D13 D5 D14 D6 D15 D7 : Palette A SEGC0 : : : Palette C SEGA131 0 1 Palette C SEGA0 Palette B SEGB0 : : Palette B SEGB131 Palette A SEGC131 Ver.2004-06-29 : : - 33 - NJU6854 Relationship among Display Data, X address and Segment Drivers(8-bit Access Mode) 1 write in data nd 2 write in data st D01 D02 D11 D12 D21 D22 D31 D32 D41 D42 D51 D52 D61 D62 D71 D72 65k-color mode, MODE[1:0]=0H REF 0 1 UDS SWAP 0 1 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D02 D01 D22 D21 D32 D31 D42 D41 D52 D51 D62 D61 D12 D11 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D72 D71 D01 D02 D11 D12 D21 D22 D31 D32 D41 D42 D51 D52 D61 D62 D71 D72 X = 83H X = 00H D02 D01 D22 D21 D32 D31 D42 D41 D52 D51 D62 D61 D72 D71 D01 D02 D11 D12 D21 D22 D31 D32 D41 D42 D51 D52 D22 D21 D61 D62 D32 D31 D71 D72 D42 D41 D12 D11 : : : : Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA131 Palette B SEGB131 Palette C SEGC131 REF 0 1 UDS SWAP 1 0 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D31 D32 D41 D42 D51 D52 D61 D62 D71 D72 D52 D51 D62 D61 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D72 D71 D01 D02 D11 D12 D21 D22 D02 D01 D22 D21 D32 D31 D42 D41 D12 D11 X = 83H X = 00H D31 D32 D41 D42 D51 D52 D61 D62 D71 D72 D52 D51 D62 D61 D72 D71 D01 D02 D11 D12 D21 D22 D02 D01 D12 D11 : : : : Palette C SEGA131 : : Palette C SEGA0 Palette B SEGB0 Palette A SEGC0 Palette B SEGB131 Palette A SEGC131 4k-color mode, MODE[1:0]=1H REF 0 1 UDS SWAP 0 1 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D22 D21 D32 D31 D42 D41 D72 D71 D12 D11 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D01 D02 D11 D12 D21 D22 D41 D42 D51 D52 D61 D62 D71 D72 X = 83H X = 00H D22 D21 D32 D31 D42 D41 D72 D71 D01 D02 D11 D12 D21 D22 D41 D42 D51 D52 D22 D21 D61 D62 D32 D31 D71 D72 D42 D41 D12 D11 : Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 : : : Palette A SEGA131 : : Palette B SEGB131 Palette C SEGC131 REF 0 1 UDS SWAP 1 0 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D41 D42 D51 D52 D61 D62 D71 D72 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D72 D71 D01 D02 D11 D12 D21 D22 D22 D21 D32 D31 D42 D41 D12 D11 X = 83H X = 00H D41 D42 D51 D52 D61 D62 D71 D72 D72 D71 D01 D02 D11 D12 D21 D22 D12 D11 : Palette A SEGC0 : : : Palette C SEGA131 0 1 Palette C SEGA0 Palette B SEGB0 : : Palette B SEGB131 Palette A SEGC131 : : - 34 - Ver.2004-06-29 NJU6854 4k-color mode, MODE[1:0]=2H REF 0 1 UDS SWAP 0 1 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D02 D01 D22 D21 D32 D31 D42 D41 D12 D11 0 1 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D52 D51 D62 D61 D72 D71 D01 D02 D11 D12 D21 D22 D31 D32 X = 83H X = 00H D02 D01 D22 D21 D32 D31 D42 D41 D52 D51 D62 D61 D72 D71 D01 D02 D11 D12 D12 D11 D21 D22 D22 D21 D31 D32 D32 D31 D12 D11 : Palette C SEGC0 : : : Palette A SEGA131 Palette A SEGA0 Palette B SEGB0 Palette B SEGB131 Palette C SEGC131 REF 0 1 UDS SWAP 1 0 IDSX 0 1 00H83H 00H83H 83H00H 83H00H D01 D02 D11 D12 D21 D22 D31 D32 X Address / Display Data / Grayscale Palette / Segment Driver X = 00H X = 83H D42 D41 D52 D51 D62 D61 D72 D71 D02 D01 D22 D21 D32 D31 D12 D11 X = 83H X = 00H D01 D02 D11 D12 D21 D22 D31 D32 D42 D41 D52 D51 D62 D61 D72 D71 D02 D01 : Palette A SEGC0 : : : Palette C SEGA131 0 1 Palette C SEGA0 Palette B SEGB0 : : Palette B SEGB131 Palette A SEGC131 Ver.2004-06-29 : : - 35 - NJU6854 (4) PWM CONTROL There are three variable grayscale modes and one fixed grayscale mode for NJU6854. In the 65k variable grayscale mode ((PWMM1,PWMM0)=(1,1)), every Aj, Bj and Cj(j=0-31) grayscale palette can select one of 32 PWM values from 128 levels(0/127~127/127). In the 4k mode, every Aj, Bj and Cj(j=0-31) grayscale palette can select one of 16 PWM values from 128 levels (0/127~127/127). Table 8 PWM and Grayscale mode PWMM1 PWMM0 Grayscale Mode 0 0 Variable 0 1 Variable 1 0 Fixed 1 1 Variable Grayscale Display Mode 32 options from 64 levels 65k-color mode, or 16 options4k-color mode 32 options from 32 levels 65k-color mode, or 16 options4k-color mode 16 options from 16 levels 4k-color mode 32 options from 128 levels 65k-color mode, or 16 options4k-color mode (5) FRAME RATE CONTROL(FRC) FRC (Frame Rate control) is the method which averages PWM value (grayscale level) by changing this value by the frame. The FRC is used for the SEGBi (palette Bj) in combination with PWM control in the 65K mode, so that the SEGBi can generate 64 grayscales (32 grayscales x 2) by total 6 bits data (5-bit PWM data and 1-bit FRC data). (6) DISPLAY TIMING GENERATOR The display timing generator generates timing clocks such as the LP (Latch Pulse), M (Frame Rate) and FLM (First Line Maker) by dividing an oscillation frequency. The LP is used for the line counter and the data latch circuit. At the rising edge of the LP signal, the line counter is counted up, then display data is latched into the data latch circuit. At the falling edge of the LP signal, the latch data is released to the grayscale control circuit, then segment drivers Ai, Bi and Ci (i=0~131) produce LCD driving waveforms. The internal data-transmission timing between the DDRAM and segment drivers is completely independent of external data-transmission timing, so that MPU makes access to the LSI without concern for the LSI's internal operation. The M toggles once every frame in the default status, and can be programmed to toggle once every N lines. And the FLM is used to specify an initial display line, which is preset whenever the FLM becomes "H". (7) DATA LATCH CIRCUIT The data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. The display data in this circuit is updated in synchronization with the LP. The "Display ON/OFF" and "Reverse Display ON/OFF" instructions control the data in this circuit, but does not change the data in the DDRAM. - 36 - Ver.2004-06-29 NJU6854 (8) COMMON DRIVERS AND SEGMENT DRIVERS The LSI includes 132-common drivers and 396-segment drivers. The common drivers generate LCD driving waveforms formed on the V0, V1, V4 and VSSH levels. The segment drivers generate waveforms formed on the V0, V2, V3 and VSSH levels. SEGC SEGB SEGA COMA0 COMA1 COMA2 LP FLM M SEGC SEGB SEGA COMA0 COMA0 COMA1 COMA2 COMA2 COMA1 SEGA SEGC SEGB SEGA SEGB COMA0 COMA1 COMA2 SEGC Fig 6 LCD Driving Waveforms (1/132Duty) Ver.2004-06-29 - 37 - NJU6854 (9) OSCILLATOR The oscillator consists of a resistor and a capacitor, and generates internal clocks for the display timing generator and the voltage booster. Through Oscillation Control register(CR), oscillating signal can be generated by using the internal resistor or an external resistor. Besides, external clock can be used too. If using the internal resistor, ground OSCI pin and keep OSCO pin open. Frequency can be adjusted or divided by using Frequency Control register(MDIV). If using the external resistor, connect OSCI and OSCO with an resistor. If using external clock, input 50% duty signal to the OSCI pin. (10) LCD POWER SUPPLY The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage converter consists of the reference voltage generator with temperature compensation circuit, the voltage regulator with EVR control and the LCD bias voltage generator. Furthermore the configuration of the LCD power supply can be arranged by setting Power Control 1 register(TCBI) and Power Control 2 register (POW2). It is possible to use part of the internal LCD power supply with an external supply, as shown in Table 17. Table 9 Configuration of LCD Power Supply AMPON VGOFF DCON VBON Voltage Booster DISABLE Voltage Converter Voltage Regulator (VREG output) DISABLE ENABLE DISABLE DISABLE ENABLE ENABLE ENALBLE DISABLE ENABLE Reference Voltage Generator (VBA output) DISABLE DISABLE DISABLE ENABLE DISABLE DISABLE ENABLE ENABLE ENABLE LCD Bias Generator DISABLE External Power Supply VOUT, V0, V1, V2, V3 and V4 are supplied VOUT, VREF are supplied VOUT, VREG are supplied VOUT is supplied VREF is supplied VREG is supplied Note 0 0 X 0 X 0 X 1 0 X 1 1 2 3 4 5 6 0 1 1 0 0 1 1 1 0 NOTE1) The LCD bias voltages are externally supplied, and C1, C2, C3, C4, C5, VREF, VREG and VEE are open. NOTE2) The VOUT and VREF are externally supplied, and the C1, C2, C3, C4, C5 and VEE are open. NOTE3) The VOUT and VREG are externally supplied, and the C1, C2, C3, C4, C5 and VEE are open. NOTE4) The VOUT is externally supplied, and the C1, C2, C3, C4 and C5 are open. NOTE5) The VREF is externally supplied. NOTE6) The VREG is externally supplied - 38 - Ver.2004-06-29 NJU6854 (10-1) Voltage Booster The internal voltage booster generates up to 6xVEE voltage. The boost level is selected from 2x~6x by setting the Boost Level register(GVU). The boost voltage VOUT must not exceed 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI. VOUT=18.0V VOUT=9V VEE=3V VSSH=0V 3-time boost VEE=3V VSSH=0V 6-time boost Fig 7 Boost Voltage 5-time Boost 6-time Boost C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH + + + + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH + + + + + 4-time Boost 3-time Boost 2-time Boost C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH + + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSSH + + Fig 8 External Capacitor Connection of Voltage Booster (10-2) Electrical Volume Register (EVR) The EVR is used to fine-tune the V0 voltage to optimize display contrast. The EVR value is controlled in 128 steps by setting the Electrical Volume register(EVOL). Ver.2004-06-29 - 39 - NJU6854 (10-3) Voltage Converter (10-3-1) Voltage Regulator The voltage regulator consists of an operational amplifier with gain control and EVR. The VREF voltage is multiplied to obtain the VREG voltage, and gain control is set by the GSEL bit of the Boost Level register (GVU). When GSEL=0, boost level is determined by VU2~VU0 bits value. When GSEL=1, booster level is determined by RG2~RG0 bit value. The relationship of VREG and LCD driving voltage(V0) is shown as below: available V0 voltage range by control VREG gain 18 16 14 12 10 8 6 4 2 VREG gain EVR =00H EVR =00H Volt EVR =7FH VREF=2.7V external reference VREF=1.9V internal reference EVR =7FH 2x 3x 4x 5x 6x 6.45 x 7x 7.3 x 8.0 x Fig 9 Relationship of V0 and VREG Table 10 VREG gain GSEL = `0' VU2 VU1 VU0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 RG2 0 0 0 0 1 1 1 1 GSEL = `1' RG1 RG0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VREG Gain 2 3 4 5 6 6.45 7 7.3 8.0 - Remark default VU[2:0] default RG[2:0] 1 1 1 1 0 1 VREG can be calculated by the following equation: VREG = VREF x N (N: Boost Level) Note) To stabilize the VREG, connect a capacitor to the VREG pin. - 40 - Ver.2004-06-29 NJU6854 (10-3-2) Reference Voltage Generator The reference voltage generator outputs about 1.9V reference voltage. When using the internal LCD power supply, connect the VBA and the VREF. When using an external LCD power supply, input external power into VREF pin and keep VBA open. The temperature compensating circuit is built in, compensation coefficient can be selected from the following shown 4 levels by setting TCV1~TVC0 bits of Power Control 1 register(TCBI). reference voltage -0.24% /C -0.20% / C -0.13% / C 1.9 -0.0% / C -30 0 Fig 10 30 Temperature Compensation 60 temperature Table 11 Temperature Coefficient Selection TCV[1] 0 0 1 1 TCV[0] 0 1 0 1 VBA Output 0.0 % /C - 0.13 % /C - 0.20 % /C - 0.24 % /C Remark Default setting (10-3-3) LCD Bias Voltage Generator The LCD bias voltage generator consists of buffer amplifiers and bleeder resistors, and the bias ratio can be selected from1/5~1/12 through setting B2~B0 bits of Power Control 1 register(TCBI). Ver.2004-06-29 - 41 - NJU6854 (10-4) External Components for LCD Power Supply Using External Power Supply Only Using Internal Power Supply VDD VEE VBA VREF VREG VSS VSS CA1 CA1 CA1 CA1 CA1 CA3 CA3 VDD VEE VBA VREF VREG C1 + C1 C2 + C2 C3 + C3 C4 + C4 C5 + C5 - C1 + C1 C2 + C2 C3 + C3 C4 + C4 C5 + C5 - NJU6854 CA1 VOUT V0 External power circuit V1 V2 V3 V4 V0 V1 V2 V3 V4 VOUT V0 V1 V2 V3 V4 VSS CA2 CA2 CA2 CA2 CA2 VSS Fig 11 Fig 12 Reference guide values of capacitor CA1 0.47 ~ 4.7 uF CA2 0.47 ~ 2.2 uF CA3 0~0.1uF NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular application. NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, V0, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI's operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. - 42 - NJU6854 Ver.2004-06-29 NJU6854 Using Internal Power Supply without Reference Voltage Generator(1) Using Internal Power Supply without Reference Voltage Generator(2) VDD VEE VBA thermistor VDD VEE VBA CA3 CA3 VSS CA1 CA1 CA1 C1 + C1 C2 + C2 C3 + C3 C4 + C4 C5 + C5 VREF VREG CA3 CA3 VSS CA1 CA1 CA1 CA1 CA1 VREF VREG C1 + C1 C2 + C2 C3 + C3 C4 + C4 C5 + C5 - NJU6854 CA1 CA1 CA1 VSS CA2 CA2 CA2 CA2 CA2 VSS CA1 VOUT V0 V1 V2 V3 V4 VSS VSS CA2 CA2 CA2 CA2 CA2 VOUT V0 V1 V2 V3 V4 Fig 11 Fig 12 Reference guide values of capacitor CA1 0.47 ~ 4.7 uF CA2 0.47 ~ 2.2 uF CA3 0~0.1uF NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular application. NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, V0, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI's operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. . Ver.2004-06-29 NJU6854 - 43 - NJU6854 Using Internal Power Supply Without Voltage Booster VDD VEE VBA CA3 VSS C1 + C1 C2 + C2 C3 + C3 C4 + C4 C5 + C5 VREF VREG External power circuit VOUT CA2 CA2 CA2 CA2 CA2 VSS V0 V1 V2 V3 V4 Fig 15 Reference guide values of capacitor CA1 0.47 ~ 4.7 uF CA2 0.47 ~ 2.2 uF CA3 0~0.1uF NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular application. NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, V0, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI's operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. NJU6854 - 44 - Ver.2004-06-29 NJU6854 (10-5) Power ON/OFF To protect the LSI from over current, the following sequences must be maintained to turn on and off the power supply. Using Internal LCD Power Supply Power ON First "VDD and VEE ON", next "Reset by RESb", then "Internal LCD power supply ON". Be sure to execute the "Display ON" instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be turned on instantly. Power OFF First "Reset by RESb or "HALT" instruction", next "VDD and VEE OFF". If using different power sources for the VDD and the VEE, the VEE must be turned off after the reset or the "HALT". After that, the VDD can be turned off, waiting until the LCD bias voltages (V0~V4) drop below the threshold level of LCD pixels. Using External LCD Power Supply Power ON First "VDD and VEE ON", next "Reset by RESb", then "External LCD power supply ON". When using only external VOUT, first "VDD ON", next "Reset by RESb", then "External VOUT ON", as well. Power OFF First "Reset by RESb or "HALT" instruction" to isolate external LCD bias voltages, next "VDD OFF". For more safety, placing a resistor in series on the V0 line (or the VOUT line in using only the external VOUT) is recommended. That resistance is usually between 50 and 100. VDD, VEE Fig 16 Rising Time of the Power Supply Item Recommended Rising Time Applicable Power tr VDD, VEE 30 ~ 100 Note : The rising time is the time from 10% VDD to 90%VEE (10-6) Discharge Circuit The LSI incorporates two independently discharge circuits for the capacitors connected to VOUT and V1-V4. When setting DSI1 bit of Discharge ON/OFF register (DISC) to "1", or executing reset instruction, the capacitors on V1-V4 are discharged, by the same way, setting DSI2 to "1" or resetting, the capacitor on VOUT is discharged. Be sure to turn off the internal or external LCD power supply during discharging, otherwise discharge circuit will function as a current load and increase operating current. Ver.2004-06-29 - 45 - NJU6854 (10-7) Reset Function The reset function initializes the LSI to the following default status by setting the RESb to "L". Usually connect the RESb to MPU's reset pin, so that the LSI and MPU are initialized simultaneously. Table 12 Default Status ITEM DDRAM Y address X address DDRAM access increment mode Bus length Initial display line Display ON/OFF Reverse display ON/OFF Display clock monitor Duty cycle ratio Vertical Blanking Area n-line Inversion ON/OFF Common scan direction REF Swap Electronic Volume Register(EVR) Internal LCD Power Supply Display mode Bias ratio Colors Select Grayscale palette Aj[6:0] Grayscale palette Bj[6:0] Grayscale palette Cj[6:0] Extra palette PCX[6:0] PWM output mode Discharge ON/OFF Initial value Undefined 00H 00H X/Y address increment ON 8bit st 0H (1 line) OFF OFF(Normal) OFF 1/132 0 OFF COMA0 COMA65 COMB0 COMB65 REF=0(Normal) OFF(Normal) (0, 0, 0, 0, 0, 0) OFF Variable grayscale mode(64 grayscales) 1/9 bias 65,536 colors Default value Default value Default value Default value Forward PWM OFF(0) - 46 - Ver.2004-06-29 NJU6854 (11) INSTRUCTION TABLES Table 0 [2:0] = 000B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name CR CFG VPC FVC ADRH ADRL EADRH EADRL COLOR MDIV HCT HST SSC1 SSC2 PCC1 PCC2 D7 * AIM1 VPC7 * XA7 YA7 XEA7 YEA7 PWMM1 * * HST7 SSC17 SSC27 PCC17 PCC27 D6 * AIM0 VPC6 * XA6 YA6 XEA6 YEA6 PWMM0 MDIV2 HCT6 HST6 SSC16 SSC26 PCC16 PCC26 D5 * VWR VPC5 * XA5 YA5 XEA5 YEA5 * MDIV1 HCT5 HST5 SSC15 SSC25 PCC15 PCC25 D4 * IDSY VPC4 * XA4 YA4 XEA4 YEA4 MODE1 MDIV0 HCT4 HST4 SSC14 SSC24 PCC14 PCC24 D3 * IDSX VPC3 FVC3 XA3 YA3 XEA3 YEA3 MODE0 * HCT3 HST3 SSC13 SSC23 PCC13 PCC23 D2 CRF WIN VPC2 FVC2 XA2 YA2 XEA2 YEA2 * CRB2 HCT2 HST2 SSC12 SSC22 PCC12 PCC22 D1 CRS1 UDS VPC1 FVC1 XA1 YA1 XEA1 YEA1 * CRB1 HCT1 HST1 SSC11 SSC21 PCC11 PCC21 D0 CRS0 SWIF VPC0 FVC0 XA0 YA0 XEA0 YEA0 MODED CRB0 HCT0 HST0 SSC10 SSC20 PCC10 PCC20 REMARK OSC control Display data Configuration /Window Area ON/OFF /Increment Control Display Line Number Blank Line Number DDRAM X address DDRAM Y address Window End X address Window End Y address Display Mode/Grayscale Mode OSC Frequency control Header COM Initial Display Line Scan Start COM 1 Scan Start COM 2 Partial Display Line Number1 Partial Display Line Number 2 Table1 [2:0] = 001B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name MC TCBI EVOL PBX * POW2 GVU BCK DISPLAY PWM ECONT DISC EDATA RA SSC3 PCC3 D7 MC7 VGOFF * MON * * GSEL BCKS REF * TST0 * LED27 RSS SSC37 PCC37 D6 MC6 VBON EVOL6 * * * RG2 BCKG SWAP * EN3PTL * LED26 RA6 SSC36 PCC36 D5 MC5 TCV1 EVOL5 * * * RG1 * * PWMC1 ENLED * LED25 RA5 SSC35 PCC35 D4 MC4 TCV0 EVOL4 GS * CKCONT RG0 * SHIFT1 PWMC0 REV * LED24 RA4 SSC34 PCC34 D3 MC3 * EVOL3 PBX3 * AMPON * BCK3 SHIFT0 PWMB1 LED13 * LED23 RA3 SSC33 PCC33 D2 MC2 B2 EVOL2 PBX2 * HALT VU2 BCK2 TBC PWMB0 LED12 * LED22 RA2 SSC32 PCC32 D1 MC1 B1 EVOL1 PBX1 * DCON VU1 BCK1 TEN PWMA1 LED11 DIS2 LED21 RA1 SSC31 PCC31 D0 MC0 B0 EVOL0 PBX0 * RES VU0 BCK0 ON/OFF PWMA0 LED10 DIS1 LED20 RA0 SSC30 PCC30 REMARK N-line Inversion Power Control 1 Electronic Volume Display Timing Signal Monitor/Grayscale palette BX N/A Power control 2 Amplifier gain/ Booster Level Booster clock Display control PWM Mode control 3 Partial Display / LED control / Rev Discharge control LED control signal Setting Instruction Table Scan Start COM 3 Partial Display Line Number3 Ver.2004-06-29 - 47 - NJU6854 Table2 [2:0] = 010B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 D7 * * * * * * * * * * * * * * * * D6 PA06 PA16 PA26 PA36 PA46 PA56 PA66 PA76 PA86 PA96 PA106 PA116 PA126 PA136 PA146 PA156 D5 PA05 PA15 PA25 PA35 PA45 PA55 PA65 PA75 PA85 PA95 PA105 PA115 PA125 PA135 PA145 PA155 D4 PA04 PA14 PA24 PA34 PA44 PA54 PA64 PA74 PA84 PA94 PA104 PA114 PA124 PA134 PA144 PA154 D3 PA03 PA13 PA23 PA33 PA43 PA53 PA63 PA73 PA83 PA93 PA103 PA113 PA123 PA133 PA143 PA153 D2 PA02 PA12 PA22 PA32 PA42 PA52 PA62 PA72 PA82 PA92 PA102 PA112 PA122 PA132 PA142 PA152 D1 PA01 PA11 PA21 PA31 PA41 PA51 PA61 PA71 PA81 PA91 PA101 PA111 PA121 PA131 PA141 PA151 D0 PA00 PA10 PA20 PA30 PA40 PA50 PA60 PA70 PA80 PA90 PA100 PA110 PA120 PA130 PA140 PA150 REMARK Grayscale palette A0 (0/31) Grayscale palette A1 (1/31) Grayscale palette A2 (2/31) Grayscale palette A3 (3/31) Grayscale palette A4 (4/31) Grayscale palette A5 (5/31) Grayscale palette A6 (6/31) Grayscale palette A7 (7/31) Grayscale palette A8 (8/31) Grayscale palette A9 (9/31) Grayscale palette A10 (10/31) Grayscale palette A11 (11/31) Grayscale palette A12 (12/31) Grayscale palette A13 (13/31) Grayscale palette A14 (14/31) Grayscale palette A15 (15/31) Table3 [2:0] = 011B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 D7 * * * * * * * * * * * * * * * * D6 PA166 PA176 PA186 PA196 PA206 PA216 PA226 PA236 PA246 PA256 PA266 PA276 PA286 PA296 PA306 PA316 D5 PA165 PA175 PA185 PA195 PA205 PA215 PA225 PA235 PA245 PA255 PA265 PA275 PA285 PA295 PA305 PA315 D4 PA164 PA174 PA184 PA194 PA204 PA214 PA224 PA234 PA244 PA254 PA264 PA274 PA284 PA294 PA304 PA314 D3 PA163 PA173 PA183 PA193 PA203 PA213 PA223 PA233 PA243 PA253 PA263 PA273 PA283 PA293 PA303 PA313 D2 PA162 PA172 PA182 PA192 PA202 PA212 PA222 PA232 PA242 PA252 PA262 PA272 PA282 PA292 PA302 PA312 D1 PA161 PA171 PA181 PA191 PA201 PA211 PA221 PA231 PA241 PA251 PA261 PA271 PA281 PA291 PA301 PA311 D0 PA160 PA170 PA180 PA190 PA200 PA210 PA220 PA230 PA240 PA250 PA260 PA270 PA280 PA290 PA300 PA310 REMARK Grayscale palette A16 (16/31) Grayscale palette A17 (17/31) Grayscale palette A18 (18/31) Grayscale palette A19 (19/31) Grayscale palette A20 (20/31) Grayscale palette A21 (21/31) Grayscale palette A22 (22/31) Grayscale palette A23 (23/31) Grayscale palette A24 (24/31) Grayscale palette A25 (25/31) Grayscale palette A26 (26/31) Grayscale palette A27 (27/31) Grayscale palette A28 (28/31) Grayscale palette A29 (29/31) Grayscale palette A30 (30/31) Grayscale palette A31 (31/31) - 48 - Ver.2004-06-29 NJU6854 Table4 [2:0] = 100B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 D7 * * * * * * * * * * * * * * * * D6 PB06 PB16 PB26 PB36 PB46 PB56 PB66 PB76 PB86 PB96 PB106 PB116 PB126 PB136 PB146 PB156 D5 PB05 PB15 PB25 PB35 PB45 PB55 PB65 PB75 PB85 PB95 PB105 PB115 PB125 PB135 PB145 PB155 D4 PB04 PB14 PB24 PB34 PB44 PB54 PB64 PB74 PB84 PB94 PB104 PB114 PB124 PB134 PB144 PB154 D3 PB03 PB13 PB23 PB33 PB43 PB53 PB63 PB73 PB83 PB93 PB103 PB113 PB123 PB133 PB143 PB153 D2 PB02 PB12 PB22 PB32 PB42 PB52 PB62 PB72 PB82 PB92 PB102 PB112 PB122 PB132 PB142 PB152 D1 PB01 PB11 PB21 PB31 PB41 PB51 PB61 PB71 PB81 PB91 PB101 PB111 PB121 PB131 PB141 PB151 D0 PB00 PB10 PB20 PB30 PB40 PB50 PB60 PB70 PB80 PB90 PB100 PB110 PB120 PB130 PB140 PB150 REMARK Grayscale palette B0 (0/31) Grayscale palette B1 (1/31) Grayscale palette B2 (2/31) Grayscale palette B3 (3/31) Grayscale palette B4 (4/31) Grayscale palette B5 (5/31) Grayscale palette B6 (6/31) Grayscale palette B7 (7/31) Grayscale palette B8 (8/31) Grayscale palette B9 (9/31) Grayscale palette B10 (10/31) Grayscale palette B11 (11/31) Grayscale palette B12 (12/31) Grayscale palette B13 (13/31) Grayscale palette B14 (14/31) Grayscale palette B15 (15/31) Table5 [2:0] = 101B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 D7 * * * * * * * * * * * * * * * * D6 PB166 PB176 PB186 PB196 PB206 PB216 PB226 PB236 PB246 PB256 PB266 PB276 PB286 PB296 PB306 PB316 D5 PB165 PB175 PB185 PB195 PB205 PB215 PB225 PB235 PB245 PB255 PB265 PB275 PB285 PB295 PB305 PB315 D4 PB164 PB174 PB184 PB194 PB204 PB214 PB224 PB234 PB244 PB254 PB264 PB274 PB284 PB294 PB304 PB314 D3 PB163 PB173 PB183 PB193 PB203 PB213 PB223 PB233 PB243 PB253 PB263 PB273 PB283 PB293 PB303 PB313 D2 PB162 PB172 PB182 PB192 PB202 PB212 PB222 PB232 PB242 PB252 PB262 PB272 PB282 PB292 PB302 PB312 D1 PB161 PB171 PB181 PB191 PB201 PB211 PB221 PB231 PB241 PB251 PB261 PB271 PB281 PB291 PB301 PB311 D0 PB160 PB170 PB180 PB190 PB200 PB210 PB220 PB230 PB240 PB250 PB260 PB270 PB280 PB290 PB300 PB310 REMARK Grayscale palette B16 (16/31) Grayscale palette B17 (17/31) Grayscale palette B18 (18/31) Grayscale palette B19 (19/31) Grayscale palette B20 (20/31) Grayscale palette B21 (21/31) Grayscale palette B22 (22/31) Grayscale palette B23 (23/31) Grayscale palette B24 (24/31) Grayscale palette B25 (25/31) Grayscale palette B26 (26/31) Grayscale palette B27 (27/31) Grayscale palette B28 (28/31) Grayscale palette B29 (29/31) Grayscale palette B30 (30/31) Grayscale palette B31 (31/31) Ver.2004-06-29 - 49 - NJU6854 Table6 [2:0] = 110B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 D7 * * * * * * * * * * * * * * * * D6 PC06 PC16 PC26 PC36 PC46 PC56 PC66 PC76 PC86 PC96 PC106 PC116 PC126 PC136 PC146 PC156 D5 PC05 PC15 PC25 PC35 PC45 PC55 PC65 PC75 PC85 PC95 PC105 PC115 PC125 PC135 PC145 PC155 D4 PC04 PC14 PC24 PC34 PC44 PC54 PC64 PC74 PC84 PC94 PC104 PC114 PC124 PC134 PC144 PC154 D3 PC03 PC13 PC23 PC33 PC43 PC53 PC63 PC73 PC83 PC93 PC103 PC113 PC123 PC133 PC143 PC153 D2 PC02 PC12 PC22 PC32 PC42 PC52 PC62 PC72 PC82 PC92 PC102 PC112 PC122 PC132 PC142 PC152 D1 PC01 PC11 PC21 PC31 PC41 PC51 PC61 PC71 PC81 PC91 PC101 PC111 PC121 PC131 PC141 PC151 D0 PC00 PC10 PC20 PC30 PC40 PC50 PC60 PC70 PC80 PC90 PC100 PC110 PC120 PC130 PC140 PC150 REMARK Grayscale palette C0 (0/31) Grayscale palette C1 (1/31) Grayscale palette C2 (2/31) Grayscale palette C3 (3/31) Grayscale palette C4 (4/31) Grayscale palette C5 (5/31) Grayscale palette C6 (6/31) Grayscale palette C7 (7/31) Grayscale palette C8 (8/31) Grayscale palette C9 (9/31) Grayscale palette C10 (10/31) Grayscale palette C11 (11/31) Grayscale palette C12 (12/31) Grayscale palette C13 (13/31) Grayscale palette C14 (14/31) Grayscale palette C15 (15/31) Table7 [2:0] = 111B RA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Name PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 D7 * * * * * * * * * * * * * * * * D6 PC166 PC176 PC186 PC196 PC206 PC216 PC226 PC236 PC246 PC256 PC266 PC276 PC286 PC296 PC306 PC316 D5 PC165 PC175 PC185 PC195 PC205 PC215 PC225 PC235 PC245 PC255 PC265 PC275 PC285 PC295 PC305 PC315 D4 PC164 PC174 PC184 PC194 PC204 PC214 PC224 PC234 PC244 PC254 PC264 PC274 PC284 PC294 PC304 PC314 D3 PC163 PC173 PC183 PC193 PC203 PC213 PC223 PC233 PC243 PC253 PC263 PC273 PC283 PC293 PC303 PC313 D2 PC162 PC172 PC182 PC192 PC202 PC212 PC222 PC232 PC242 PC252 PC262 PC272 PC282 PC292 PC302 PC312 D1 PC161 PC171 PC181 PC191 PC201 PC211 PC221 PC231 PC241 PC251 PC261 PC271 PC281 PC291 PC301 PC311 D0 PC160 PC170 PC180 PC190 PC200 PC210 PC220 PC230 PC240 PC250 PC260 PC270 PC280 PC290 PC300 PC310 REMARK Grayscale palette C16 (16/31) Grayscale palette C17 (17/31) Grayscale palette C18 (18/31) Grayscale palette C19 (19/31) Grayscale palette C20 (20/31) Grayscale palette C21 (21/31) Grayscale palette C22 (22/31) Grayscale palette C23 (23/31) Grayscale palette C24 (24/31) Grayscale palette C25 (25/31) Grayscale palette C26 (26/31) Grayscale palette C27 (27/31) Grayscale palette C28 (28/31) Grayscale palette C29 (29/31) Grayscale palette C30 (30/31) Grayscale palette C31 (31/31) - 50 - Ver.2004-06-29 NJU6854 (12) INSTRUCTION DESCRIPTIONS (12-1) 8-bit Access Mode Set MSB bit of the 1st byte to "0". Data to instruction register is transferred in 2 bytes, For the 1st byte, D6~D4 is used to set the instruction table address, and D3~D0 to set instruction register address. The 2nd byte is instruction data. MSB 0 LSB Instruction Register Address st (12-1-1) Instruction Register Instruction Table Address data 1 access 2 access nd (Example) X, Y address of DDRAM Step 1: 1 byte(X address) D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0 CSb 0 RS 1 RDb 1 WRb 0 st 0 Step 2: 2 nd Table address D6 XA6 D5 XA5 D4 XA4 Register address D3 XA3 D2 XA2 D1 XA1 D0 XA0 CSb 0 Pins setting RS 1 RDb 1 WRb 0 byte(X address) D7 XA7 Step 3: 1 byte(Y address) D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 1 CSb 0 RS 1 RDb 1 WRb 0 st 0 Step 4: 2 nd Table address D6 YA6 D5 YA5 D4 YA4 Register address D3 YA3 D2 YA2 D1 YA1 D0 YA0 CSb 0 Pins setting RS 1 RDb 1 WRb 0 byte(Y address). D7 YA7 Ver.2004-06-29 - 51 - NJU6854 By setting MSB bit of the 1st byte to "1", instruction data can be written to the registers successively. For the 1st byte, D6~D4 is used to set the instruction table address(Table[2:0]) and D3~D0 to set the count number for the registers, from the 2nd byte, data will be automatically written to the successive registers. MSB 1 LSB Table address Count number(n) count 1 count 2 data of address 0 data of address 1 . . . . . data of address n-1 (12-1-2) Auto-increment of Instruction Register Address count n If the counter number is set as 0, data is written to the registers from the address 0 to 15. (Example) Oscillator and others. Step 1: 8bit auto increment / table address set / count number D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 1 CSb 0 RS 1 RDb 1 WRb 0 1 D7 * Table address D6 * D5 * D4 * count number = 5 D3 * D2 CRF Pins setting CSb 0 Step 2: 8bit auto increment / count = 1 D1 CRS1 D0 CRS0 RS 1 RDb 1 WRb 0 Step 3: 8 bit auto increment / count = 2 D7 AIM1 D6 AIM0 D5 VWR D4 IDSY D3 IDSX D2 WIN D1 UDS D0 SWIF CSb 0 RS 1 RDb 1 WRb 0 Step 4: 8 bit auto increment / count = 3 D7 VPC7 D6 VPC6 D5 VPC5 D4 VPC4 D3 VPC3 D2 VPC2 D1 VPC1 D0 VPC0 CSb 0 RS 1 RDb 1 WRb 0 Step 5: 8 bit auto increment / count = 4 D7 * D6 * D5 * D4 * D3 FVC3 D2 FVC2 D1 FVC1 D0 FVC0 CSb 0 RS 1 RDb 1 WRb 0 Step 6: 8 bit auto increment / count = 5 D7 XA7 D6 XA6 D5 XA5 D4 XA4 D3 XA3 D2 XA2 D1 XA1 D0 XA0 CSb 0 RS 1 RDb 1 WRb 0 - 52 - Ver.2004-06-29 NJU6854 (12-2) 16-bit Access Mode (12-2-1) Instruction Register Set MSB bit to"0". Instruction table number, instruction register address and instruction data will be transferred in one 16-bit data. Instruction table number is determined by D14~D12, instruction register is determined by D11~D8, and D7~D0 is instruction data. MSB 0 LSB Table address Register address Instruction data (Example) X, Y address of DDRAM Step 1: X address setting. D15 0 D14 0 D13 0 D12 0 D11 0 D10 1 D9 0 D8 0 D7 XA7 D6 XA6 D5 XA5 D4 XA4 D3 XA3 D2 XA2 D1 XA1 D0 XA0 0 D15 0 Table address D14 0 D13 0 D12 0 Register address D11 0 D10 1 D9 0 D8 1 D7 YA7 D6 YA6 D5 YA5 data D4 YA4 D3 YA3 D2 YA2 D1 YA1 D0 YA0 Step 1: Y address setting 0 Table address Register address data By setting MSB bit of the 1st byte to "1", instruction data can be written to the registers successively. For the 1st byte, only upper 8-bit data is valid, D14~D12 is used to set the instruction table number(Table[2:0]) and D11~D8 to set the count number of the registers. From the 2nd byte, data will be automatically written to the successive registers. MSB 1 Table address LSB Count number(n) data of address 1 data of address 3 .. . . data of address n-1 (12-2-2) Auto Increment of Instruction Register Address data of address 0 data of address 2 .. . . data of address n-2 If count number is 0, data is written to the registers from the address 0 to 15. (Example) Oscillator and Configuration control Step 1: D15 1 D14 0 D13 0 D12 0 D11 0 D10 1 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * 1 Step 2: D15 * Table address D14 * D13 * D12 * count number = 5 D11 * D10 CRF data (don't care ) D7 AIM1 D9 CRS1 D8 CRS0 D6 AIM0 D5 VWR D4 IDSY D3 IDSX D2 WIN D1 UDS D0 SWIF Step 3: D15 VPC7 D14 VPC6 D13 VPC5 D12 VPC4 D11 VPC3 D10 VPC2 D9 VPC1 D8 VPC0 D7 * D6 * D5 * D4 * D3 FVC3 D2 FVC2 D1 FVC1 D0 FVC0 Step 4: D15 XA7 D14 XA6 D13 XA5 D12 XA4 D11 XA3 D10 XA2 D9 XA1 D8 XA0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * (*: not applicable) Ver.2004-06-29 - 53 - NJU6854 (12-3) Oscillation Control Register : CR Table0 [0H] D7 * D6 * D5 * D4 * D3 * D2 CRF D1 CRS1 D0 CRS0 CSb 0 RS 1 RDb 1 WRb 0 (default: {CRF, CRS1, CRS0} = 0H, address: 0H) Setting Frequency CRF 0 0 0 0 1 1 1 1 CRS1 0 0 1 1 0 0 1 1 CRS0 0 1 0 1 0 1 0 1 Function OSCI (730 kHz) OSC2 (170 kHz) OSC5 (external R, external source) Invalid OSC3 (1,200 kHz) OSC4 (285 kHz) Invalid Invalid In OSC5 mode, connect the OSCI pin and the OSCO pin with a resistor, and input external clock signal to OSCI. (12-4) Display Data Assignment/ Window Area ONOFF/Increment Control Register: CFG / Table 0 [1H] D7 AIM1 D6 AIM0 D5 VWR D4 IDSY D3 IDSX D2 WIN D1 UDS D0 SWIF CSb 0 RS 1 RDb 1 WRb 0 (default: {AIM1, AIM0, VWR, IDSY, ISDX, WIN, UDS, SWIF} = 0H, address: 1H) (i) SWIF SWIF 0 1 Bus length 8bit I/F (Initial Value) 16bit I/F (ii) UDS Assignment of MPU data on the DDRAM 16 Bit I/F Access UDS = "0": the lower 8-bit MPU data corresponding to the lower 8-bit display data the upper 8-bit MPU data corresponding to the upper 8-bit display data UDS = "1": the lower 8-bit MPU data corresponding to the upper 8-bit display data the upper 8-bit MPU data corresponding to the lower 8-bit display data 8 Bit I/F Access UDS = "0": 1st MPU data corresponding to the lower 8-bit display data 2nd MPU data corresponding to the upper 8-bit display data UDS = "1": 1st MPU data corresponding to the upper 8-bit display data 2nd MPU data corresponding to the lower 8-bit display data (iii) WIN WIN = "1" : Window area ON WIN = "0" : Window area OFF(default) (iv) IDSX X address auto increment/auto decrement IDSX = "0" : auto increment IDSX = "1" : auto decrement (v) IDSY Y address auto increment/auto decrement IDSY = "0" : auto increment IDSY = "1" : auto decrement - 54 Ver.2004-06-29 NJU6854 (vi) VWR Setting the direction of data write /read to DDRAM VWR = "0" : start from X direction VWR = "1" : start from Y direction (vii) AIM[1:0] AIM1 0 0 1 1 AIM0 0 1 0 1 Auto increment/decrement during data writing and reading Auto increment/decrement during data writing Auto increment/decrement OFF Prohibited (12-5) Display Line Number Register: VPC TABLE0 [2H] D7 VPC7 D6 VPC6 D5 VPC5 D4 VPC4 D3 VPC3 D2 VPC2 D1 VPC1 D0 VPC0 CSb 0 RS 1 RDb 1 WRb 0 (default: VPC[7:0] = 84H, address: 2H) VPC[7:0]: display line number (displayed pixel number in Y direction). Setting within the range of 2~13202H~84H VPC7 0 0 0 0 0 0 1 1 1 1 1 VPC6 0 0 0 0 0 0 0 0 0 0 1 VPC5 0 0 0 0 0 0 0 0 0 0 1 VPC4 0 0 0 0 0 0 : 0 0 0 0 : 1 1 1 1 1 Forbidden 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 130 131 132 Forbidden VPC3 0 0 0 0 0 0 VPC2 0 0 0 0 1 1 VPC1 0 0 1 1 0 0 VPC0 0 1 0 1 0 1 Vertical Pixel Number Forbidden Forbidden 2 3 4 5 (12-6) Blank Line Number Register : FVC TABLE0 [3H] D7 * D6 * D5 * D4 * D3 FVC3 D2 FVC2 D1 FVC1 D0 FVC0 CSb 0 RS 1 RDb 1 WRb 0 (default: FVC[3:0]=0H, address: 3H) FVC[3:0]: Blank line number(not displayed pixel number in Y direction) FVC3 0 0 1 1 FVC2 0 0 : 1 1 1 1 0 1 14 15 FVC1 0 0 FVC0 0 1 Vertical blanking Lines 0 1 Ver.2004-06-29 - 55 - NJU6854 (12-7) X Address Register : ADRH TABLE0 [4H] D7 XA7 D6 XA6 D5 XA5 D4 XA4 D3 XA3 D2 XA2 D1 XA1 D0 XA0 CSb 0 RS 1 RDb 1 WRb 0 (default: XA[7:0] = 0H, address: 4H) X address range is from 00H to 83H. (12-8) Y Address Register : ADRL TABLE0 [5H] D7 YA7 D6 YA6 D5 YA5 D4 YA4 D3 YA3 D2 YA2 D1 YA1 D0 YA0 CSb 0 RS 1 RDb 1 WRb 0 (default: YA[7:0] = 0H, address: 5H) Y address range is from 00H to 83H. (12-9) Window End X Address Register : EADRH TABLE0 [6H] D7 XEA7 D6 XEA6 D5 XEA5 D4 XEA4 D3 XEA3 D2 XEA2 D1 XEA1 D0 XEA0 CSb 0 RS 1 RDb 1 WRb 0 (default: XEA[7:0] = 0H, address: 6H) Setting X address of window area when window area access is valid(WIN="1"). (12-10) Window End Y Address Register : EADRL TABLE0 [7H] D7 YEA7 D6 YEA6 D5 YEA5 D4 YEA4 D3 YEA3 D2 YEA2 D1 YEA1 D0 YEA0 CSb 0 RS 1 RDb 1 WRb 0 (default: YEA[7:0] = 0H, address: 7H) Setting Y address of window area when window area access is valid(WIN="1"). (12-11) Display Mode/Grayscale Mode Register : COLOR TABLE0 [8H] D7 D6 PWMM1 PWMM0 D5 * D4 D3 MODE1 MODE0 D2 * D1 * D0 MODED CSb 0 RS 1 RDb 1 WRb 0 (default: PWMM[1:0], MODE[1:0], MODED = 0H, address: 8H) (i) MODED Setting 65k-color or 4k-color display mode MODED 0 1 Display Color Mode 65,536 Colors Mode (PWM 5bit + 2 FRC) 4,096 Colors(4bit PWM only) (ii) MODE[1:0] Bit assignment of display data MODE[1:0] MODE1 MODE0 D15 D14 D13 D12 D11 D10 Input data D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Remark (1) 0 0 1 1 0 1 0 1 C4 C3 C3 C2 C2 C1 C1 C0 C0 C3 B5 B3 C2 B4 B2 C1 B3 B1 C0 B2 B0 B3 B1 B2 B0 B1 A4 A3 B0 A3 A2 A3 A2 A1 A2 A1 A0 A1 A0 Note (2) Note (3) A0 Note Invalid Note (1) 65,536 colors 5-6-5 data (2) 4,096 colors 4-4-4 data (3) 4,096 colors4-4-4 data, upper 4 bits invalid - 56 - Ver.2004-06-29 NJU6854 (iii) PWMM[1:0] Setting grayscale mode through PWM control. PWMM1 0 0 1 1 PWMM0 0 1 0 1 Select 32 grayscales Select 32 grayscales Select 16 grayscales Select 32 grayscales Grayscale Mode 65k mode or 16 grayscales 4k mode from 64 levels. 65k mode or 16 grayscales 4k mode from 32 levels. 4k mode from 16 levels. 65k mode or 16 grayscales 4k mode from 128 levels. Using PWM control (PWMM[1:0]) and Frame rate control(FRC), the following display mode can be selected. MODED 0 1 Display Mode 65,536 color mode 4,096 color mode FRC control 2 scan unavailable 64 grayscales base 32 grayscales selectable 16 grayscales selectable PWM control 32 grayscales 16 grayscales base base 32grayscales Forbidden selectable 16 grayscales 16 grayscales selectable selectable 128 grayscales base 32 grayscales selectable 16 grayscales selectable The relationship among the oscillating circuit, built-in clock and frame frequency Original source clock OSCI,OSC2,OSC3,OSC4,OSC5(external) selection Internal oscillator resistor selection(0.7~1.3xR) CRF,CRS[1:0] register CRB[2:0] register GCK(Source clock for grayscale signal) signal generator Frequency dividing ratio selection (1/1~1/8) MDIV[2:0] register BCKG GCK LP(Latch Pulse) signal generator Decided by dividing rate(1/127,63,31,15) PWMM[1:0], MODED Duty set Decided by VPC or (PPC1+PPC2) or (PPC1+PPC2+PPC3) : 1/2~1/132 LP BCKG LP Selection one VPC,PPC1,PPC2,PPC3 Vertical blanking line set Number of inserted LP pulse(0~15) FVC[3:0] FLM Source clock for DCDC booster Booster clock making BCK[3:0] FVC[3:0] Booster clock BLANK CKCONT OSC CRB[2:0] CRF CRS[1:0] MDIV MDIV[2:0] 1/127,63,31,15 PWMM[1:0] 1/duty + FLM VPC, PPC1,PPC2,PPC3 LP GCK 0 0 BCK 1/8 1 BCKG BCKG 1 BCKS BCKS booster clock BCK[3:0] Fig 17 Block Diagram of Oscillator Frame Duty = 1 / (duty + blank) Ver.2004-06-29 - 57 - NJU6854 PWM duty vs. display mode Display mode 65,536 color mode 4,096 color mode MODED 0 1 PWMM=00 variable 1/63 1/63 PWM control PWMM=01 PWMM=10 variable fixed 1/31 Forbidden 1/31 1/15 PWMM=11 variable 1/127 1/127 Frame frequency vs. display mode Usage Oscillator 1 1200 kHz GCK Display mode Grayscale mode ( PWMM[1:0] ) Duty Blank Equation *1) 0 FLM=1200kHz/(1x127x(132+ 0))=72Hz 1/1 Among 65,536 color Variable 1/132 undivided 128 5 FLM=1200kHz/(1x127x(132+ 5))=69Hz 0 FLM=285kHz/(1x31x(132+ 0))=70Hz 1/1 Among 2 285 kHz 4,096 color Variable 1/132 undivided 32 10 FLM=285kHz/(1x31x(132+10))=65Hz 0 FLM=170kHz/(1x15x(132+ 0))=86Hz 1/1 Among 3 170 kHz 4,096 color Fixed 1/132 undivided 32 15 FLM=170kHz/(1x15x(132+15))=77Hz 0 FLM=730kHz/(1x63x(132+ 0))=88Hz 1/1 Among 4 730 kHz 65,536 color Variable 1/132 undivided 64 8 FLM=730kHz/(1x63x(132+ 8))=83Hz NOTE): FLM: frame frequency = fOSC / (MDIV(1,2,3,4,5,6,7,8) x PWMM(15,31,63,127) x (Duty + Blank)) - 58 - Ver.2004-06-29 NJU6854 65k Colors Display Mode Display data and grayscale palette. A4 B5 C4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 B4 C3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Display RAM data A2 A1 B3 B2 C2 C1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A0 B1 C0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A/C 32 gray GS=X PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Grayscale by PWM + FRC B 64 gray (1) GS=1 PB0 PB0 ( PB0 + PB1 ) / 2 PB1 ( PB1 + PB2 ) / 2 PB2 ( PB2 + PB3 ) / 2 PB3 ( PB3 + PB4 ) / 2 PB4 ( PB4 + PB5 ) / 2 PB5 ( PB5 + PB6 ) / 2 PB6 ( PB6 + PB7 ) / 2 PB7 ( PB7 + PB8 ) / 2 PB8 ( PB8 + PB9 ) / 2 PB9 ( PB9 + PB10 ) / 2 PB10 ( PB10 + PB11 ) / 2 PB11 ( PB11 + PB12 ) / 2 PB12 ( PB12 + PB13 ) / 2 PB13 ( PB13 + PB14 ) / 2 PB14 ( PB14 + PB15 ) / 2 PB15 ( PB15 + PB16 ) / 2 PB16 ( PB16 + PB17 ) / 2 PB17 ( PB17 + PB18 ) / 2 PB18 ( PB18 + PB19 ) / 2 PB19 ( PB19 + PB20 ) / 2 PB20 ( PB20 + PB21 ) / 2 PB21 ( PB21 + PB22 ) / 2 PB22 ( PB22 + PB23 ) / 2 PB23 ( PB23 + PB24 ) / 2 PB24 ( PB24 + PB25 ) / 2 PB25 ( PB25 + PB26 ) / 2 PB26 ( PB26 + PB27 ) / 2 PB27 ( PB27 + PB28 ) / 2 PB28 ( PB28 + PB29 ) / 2 PB29 ( PB29 + PB30 ) / 2 PB30 ( PB30 + PB31 ) / 2 PB31 GS=0 PB0 PBX ( PB0 + PB1 ) / 2 PB1 ( PB1 + PB2 ) / 2 PB2 ( PB2 + PB3 ) / 2 PB3 ( PB3 + PB4 ) / 2 PB4 ( PB4 + PB5 ) / 2 PB5 ( PB5 + PB6 ) / 2 PB6 ( PB6 + PB7 ) / 2 PB7 ( PB7 + PB8 ) / 2 PB8 ( PB8 + PB9 ) / 2 PB9 ( PB9 + PB10 ) / 2 PB10 ( PB10 + PB11 ) / 2 PB11 ( PB11 + PB12 ) / 2 PB12 ( PB12 + PB13 ) / 2 PB13 ( PB13 + PB14 ) / 2 PB14 ( PB14 + PB15 ) / 2 PB15 ( PB15 + PB16 ) / 2 PB16 ( PB16 + PB17 ) / 2 PB17 ( PB17 + PB18 ) / 2 PB18 ( PB18 + PB19 ) / 2 PB19 ( PB19 + PB20 ) / 2 PB20 ( PB20 + PB21 ) / 2 PB21 ( PB21 + PB22 ) / 2 PB22 ( PB22 + PB23 ) / 2 PB23 ( PB23 + PB24 ) / 2 PB24 ( PB24 + PB25 ) / 2 PB25 ( PB25 + PB26 ) / 2 PB26 ( PB26 + PB27 ) / 2 PB27 ( PB27 + PB28 ) / 2 PB28 ( PB28 + PB29 ) / 2 PB29 ( PB29 + PB30 ) / 2 PB30 ( PB30 + PB31 ) / 2 PB31 C/A 32 gray GS=X PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Note1) 5 bits for PWM control and 1 bit for Frame rate control(total 6 bits display data), SEGBi can realize 64-grayscale (32-grayscalex2) display. Note2) Real 64-grayscael can be realized by setting PBX bit(GS="0"). Ver.2004-06-29 - 59 - NJU6854 4k Colors Display Mode Display data and grayscale palette. Display RAM data A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 A/C 16 gray GS=X PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 Grayscale by PWM B 16 gray GS=X PB1 PB3 PB5 PB7 PB9 PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 C/A 16 gray GS=X PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 PC17 PC19 PC21 PC23 PC25 PC27 PC29 PC31 Note) Under 4k colors display mode, GS bit is invalid. (12-12) Oscillating Frequency Adjustment/Frequency Dividing Register : MDIV TABLE0 [9H] D7 * D6 D5 MDIV2 MDIV1 D4 MDIV0 D3 * D2 CRB2 D1 CRB1 D0 CRB0 CSb 0 RS 1 RDb 1 WRb 0 (default: MDIV[2:0], CRB[2:0] = 0H, address : 9H) (i) CRB[2:0] Frame frequency can be modified by adjusting the resistor of oscillating circuit. Relationship between RF and Resistance ratio CRB2 0 0 0 0 1 1 1 1 CRB1 0 0 1 1 0 0 1 1 CRB0 0 1 0 1 0 1 0 1 Status Initial Resistance Ratio 1.1 times of Initial Resistance Ratio 1.2 times of Initial Resistance Ratio 1.3 times of Initial Resistance Ratio 0.9 times of Initial Resistance Ratio 0.8 times of Initial Resistance Ratio 0.7 times of Initial Resistance Ratio Forbidden (ii) MDIV[2:0] Oscillating Frequency or external clock frequency can be divided. MDIV2 0 0 0 0 1 1 1 1 MDIV1 0 0 1 1 0 0 1 1 MDIV0 0 1 0 1 0 1 0 1 Divide Ratio 1/1 dividing 1/2 dividing 1/3 dividing 1/4 dividing 1/5 dividing 1/6 dividing 1/7 dividing 1/8 dividing - 60 - Ver.2004-06-29 NJU6854 (12-13) Header COM Register : HCT TABLE0 [AH] D7 * D6 HCT6 D5 HCT5 D4 HCT4 D3 HCT3 D2 HCT2 D1 HCT1 D0 HCT0 CSb 0 RS 1 RDb 1 WRb 0 (default: HCT [6:0] = 0H, address: AH) For small panel size(row number is less than 132), this instruction is used to decide Header COM position to specify available COM drivers. The setting range is from COMA0/COMB0 ~ COMA65/COMB65. Refer to "(13) Relationship Between Logic COM Number and Physical COM Driver" for details. Note that this instruction is not used to specify a scan start position, The scan start position is decided by the "Scan Start COM 1~3". 0 HCT (132-VPC)/2 HCT6 0 0 0 0 0 0 0 0 1 1 1 1 HCT5 0 0 0 0 0 0 1 1 0 0 0 1 HCT4 0 0 0 0 0 0 1 1 0 0 0 1 HCT3 0 0 0 0 0 0 *** 1 1 0 0 0 *** 1 HCT2 0 0 0 0 1 1 1 1 0 0 0 1 HCT1 0 0 1 1 0 0 1 1 0 0 1 1 HCT0 0 1 0 1 0 1 0 1 0 1 0 1 Header COM COMA0/COMB0 COMA1/COMB1 COMA2/COMB2 COMA3/COMB3 COMA4/COMB4 COMA5/COMB5 *** COMA62/COMB62 COMA63/COMB63 COMA64/COMB64 COMA65/COMB65 Forbidden *** Forbidden (12-14) Initial Display Line Register : HST TABLE0 [BH] D7 HST7 D6 HST6 D5 HST5 D4 HST4 D3 HST3 D2 HST2 D1 HST1 D0 HST0 CSb 0 RS 1 RDb 1 WRb 0 (default : HST[7:0] = 0H, address: BH) This instruction sets the DDRAM Y address, and the addressed RAM data will be displayed by the scan start COM 1 driver. The available Y address range is from 0~131. HST7 0 0 0 0 0 0 0 0 1 1 1 1 HST6 0 0 0 0 0 0 1 1 0 0 0 1 HST5 0 0 0 0 0 0 1 1 0 0 0 1 HST4 0 0 0 0 0 0 *** 1 1 0 0 0 *** 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 HST3 0 0 0 0 0 0 HST2 0 0 0 0 1 1 HST1 0 0 1 1 0 0 HST0 0 1 0 1 0 1 Y address 0 1 2 3 4 5 : 128 129 130 131 Forbidden *** Forbidden Ver.2004-06-29 - 61 - NJU6854 (12-15) Scan Start COM 1 Register : SSC1 TABLE0 [CH] D7 D6 D5 D4 D3 SSC17 SSC16 SSC15 SSC14 SSC13 D2 D1 SSC12 SSC11 D0 SSC10 CSb 0 RS 1 RDb 1 WRb 0 (default : SSC1[7:0] = 0H, address: CH) Totally three partial area can be display on the screen once time. This instruction sets the logical number of the scan start COM driver for the full screen display or for the first partial display. Refer to (13) Relationship between logical COM number and physical COM driver for details. The available setting range is: 0 SSC1 (VPC - 1) (12-16) Scan Start COM 2 Register : SSC2 TABLE0 [DH] D7 D6 D5 D4 D3 SSC27 SSC26 SSC25 SSC24 SSC23 D2 D1 SSC22 SSC21 D0 SSC20 CSb 0 RS 1 RDb 1 WRb 0 (default : SSC2[7:0] = 0H, address: DH) This instruction sets the logical number of the scan start COM driver for the second partial display. Refer to (13) Relationship between logical COM number and physical COM driver for details. The available setting range is: SSC1+PCC1 SSC2 (VPC - 1) (12-17) Line Number of Partial Display 1 Register : PCC1 TABLE0 [EH] D7 D6 D5 D4 D3 D2 D1 D0 PCC17 PCC16 PCC15 PCC14 PCC13 PCC12 PCC11 PCC10 CSb 0 RS 1 RDb 1 WRb 0 (default : PCC1[7:0] = 0H, address: EH) This instruction sets line number(DDRAM Y address range) for the first partial display. In the partial display mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display duty. The available setting range is: 0 PCC1 (VPC - SSC1) (12-18) Line Number of Partial Display 2 Register : PCC2 TABLE0 [FH] D7 D6 D5 D4 D3 D2 D1 D0 PCC27 PCC26 PCC25 PCC24 PCC23 PCC22 PCC21 PCC20 CSb 0 RS 1 RDb 1 WRb 0 (default : PCC2[7:0] = 0H, address: FH) This instruction sets line number(DDRAM Y address range) for the second partial display. In the partial display mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display duty. The available setting range is: 0 PCC2 (VPC - SSC2). (12-19) N-Line Inversion Register : MC TABLE1 [0H] D7 MC7 D6 MC6 D5 MC5 D4 MC4 D3 MC3 D2 MC2 D1 MC1 D0 MC0 CSb 0 RS 1 RDb 1 WRb 0 (default : MC[7:0] = 0H, address: 0H) This instruction can let LCD driving signal polarity (M signal) to be alternated every N(2= - 62 - Ver.2004-06-29 NJU6854 (i) Frame Inversion (1/132 DUTY) 1st line 2nd line 3rd line 131st line132nd line 1st line LP FLM M (ii) N Line Inversion 1 st line 2nd line nth line cycle 3rd line n-1th line nth line 1 st line LP FLM M (12-20) Power Control 1 Register : TCBI TABLE1 [1H] D7 D6 VGOFF VBON D5 TCV1 D4 TCV0 D3 * D2 B2 D1 B1 D0 B0 CSb 0 RS 1 RDb 1 WRb 0 (default: VGOFF, VBON, TCV[1:0] = 0H, B[2:0] = 4H, address: 1H) (i)VGOFF Voltage Regulator (VREG output) ON/OFF VG OFF = 0: AMPON="1", Voltage Regulator ON VG OFF = 1: Voltage Regulator OFF (ii)VBON Reference Voltage Generator (VBA output) ON/OFF VBON = 0: Reference Voltage Circuit OFF VBON = 1: AMPON="1" & VGOFF="0", Reference Voltage Circuit ON (iii)TCV[1:0] Setting temperature compensation coefficient for Reference Voltage Circuit. TCV[1] TCV[0] VBA output remark 0 0 Default setting 0.0 % /C 0 1 - 0.13 % /C 1 0 - 0.20 % /C 1 1 - 0.24 % /C Ver.2004-06-29 - 63 - NJU6854 (iv) B[2:0] LCD Bias Ratio B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Function 1/5 Bias 1/6 Bias 1/7 Bias 1/8 Bias 1/9 Bias (Initial state) 1/10 Bias 1/11 Bias 1/12 Bias (12-21) Electronic Volume Control Register: EVOL TABLE1 [2H] D7 * D6 D5 D4 D3 D2 D1 D0 EVOL6 EVOL5 EVOL4 EVOL3 EVOL2 EVOL1 EVOL0 CSb 0 RS 1 RDb 1 WRb 0 (default: EVOL[6:0] = 0H, address: 2H) 128 steps available EVOL6 0 0 1 1 EVOL5 0 0 1 1 EVOL4 0 0 1 1 EVOL3 0 0 *** 1 1 EVOL2 0 0 1 1 EVOL1 0 0 1 1 EVOL0 0 1 0 1 Output Voltage Lower *** Higher VREG can be calculated from the equation (1) VREG = VREF x N ..............................................................................................................(1) (N determined by VU[2:0](boost level), RG[2:0] and GSEL bits of GVU register) LCD driving voltage V0 can be calculated from the equation (2) V0 = 0.5 x VREG + M x (VREG - 0.5 VREG) / 127 .............................. ................(2) (electronic volume M determined by EVOL[6:0] bits of EVOL register) (12-22) Display Timing Signal Monitor/PBX Palette Register : PBX TABLE1 [3H] D7 MON D6 * D5 * D4 GS D3 PBX3 D2 PBX2 D1 PBX1 D0 PBX0 CSb 0 RS 1 RDb 1 WRb 0 (default: MON, GS = 0H, PBX[3:0] = 3H, address: 3H) (i) MON Setting FLM, LP and M signals output ON/OFF MON 0 1 Function FLM, LP, M signal output OFFdefault FLM, LP, M signal output ON (ii) GS, PBX[3:0] When GS="0", palette PBX setting is available. When GS="1", PB0 is selected. GS=1 PBX[3:0] register invalid (Note 1) GS=0 0 0 0 PBX3 PBX2 PBX1 PBX0 Note 1) Under 65k colors mode , palette PBX is selected to set B data. PBX is used to display the grayscale between PB0 and PB1. - 64 - Ver.2004-06-29 NJU6854 (12-23) Power Control 2 Register : POW2 TABLE1 [5H] D7 * D6 * D5 * D4 D3 CKCONT AMPON D2 HALT D1 DCON D0 RES CSb 0 RS 1 RDb 1 WRb 0 (default: CKCONT, AMPON, HALT, DCON, RES = 0H, address: 5H) (i) RES RES = "0": Default RES = "1": Initialization Note 1) After initialization(RES="1"), RES bit turn to "0". Note 2) After initialization, at least two LP signal cycles is needed to wait to execute the next instruction. (ii) DCON Setting voltage booster ON/OFF. DCON= "0": voltage booster OFF DCON= "1": voltage booster ON (iii) HALT Setting power save mode ON/OFF HALT = "0": power save mode OFF(default) HALT = "1": power save mode ON LSI Internal status under power save mode: a. Internal oscillator and LCD power supply is in the halted state. b. COM/SEG outputs VSSH level voltage. c. External clock is unacceptable. d. DDRAM data is remained e. Instruction Register data is remained (iv) AMPON Using together with VGOFF and VBON bits of Power control 1register (TCBI) to set voltage converter ON/OFF. AMPON = "0" voltage converter OFF AMPON = "1": voltage converter ON (v) CKCONT Setting GCK signal and LP signal ON/OFF CKCONT = "0": GCK and LP OFF CKCONT = "1": GCK and LP ON Note) NJU6854 use internal oscillator or external clock signal to generate GCK and LP signal. Not only used as display clock, GCK and LP are also used as operating clock for voltage booster. Be sure to set CKCONT="1" when voltage booster is used(DCON= "1"). Ver.2004-06-29 - 65 - NJU6854 (12-24) Booster Level/Amplifier Gain Register : GVU TABLE1 [6H] D7 GSEL D6 RG2 D5 RG1 D4 RG0 D3 * D2 VU2 D1 VU1 D0 VU0 CSb 0 RS 1 RDb 1 WRb 0 (default: GSEL, RG[2:0] = 0H, VU[2:0] = 0H, address: 6H) (i) GSEL Setting amplifier gain of VREG GSEL = 0: Amplifier gain is determined by VU[2:0] bits as the same as the boost level. GSEL = 1: Amplifier gain is determined by RG[2:0] bits (ii)RG[2:0] When GSEL="1", the relationship between RG[2:0] and amplifier gain is showed as below. VU2 0 0 0 0 1 1 GSEL = `0' VU1 0 0 1 1 0 0 VU0 0 1 0 1 0 1 RG2 0 0 0 0 1 1 1 1 GSEL = `1' RG1 0 0 1 1 0 0 1 1 RG0 0 1 0 1 0 1 0 1 Amplifier gain (N) 2 3 4 5 6 6.45 7 7.3 8.0 Remark default VU[2:0] default RG[2:0] 1 1 1 1 0 1 (iii) VU[2:0] Setting boost level. And when GSEL="0", also setting amplifier gain of VREG. VU2 0 0 0 0 1 1 1 1 VU1 0 0 1 1 0 0 1 1 VU0 0 1 0 1 0 1 0 1 Function No Boost Up 2 Times Boost Up 3 Times Boost Up 4 Times Boost Up 5 Times Boost Up 6 Times Boost Up Forbidden Forbidden - 66 - Ver.2004-06-29 NJU6854 (12-25) Voltage Booster Clock Register : BCK TABLE1 [7H] D7 BCKS D6 BCKG D5 * D4 * D3 BCK3 D2 BCK2 D1 BCK1 D0 BCK0 CSb 0 RS 1 RDb 1 WRb 0 (default: BCKS, BCKG, BCK[3:0] = 0H, address: 7H) Note) NJU6854 use internal oscillator or external clock to generate GCK and LP signal. Not only used as display clock, GCK and LP are also used as operating clock for voltage booster. Be sure to set CKCONT="1" when voltage booster is used(DCON= "1"). (i) BCK[3:0] Setting dividing ratio for the oscillating signal or external clock to generate GCK and LP. BCK3 0 0 0 0 0 *** 1 1 1 1 1 BCK2 0 0 0 0 1 0 1 1 1 1 BCK1 0 0 1 1 0 1 0 0 1 1 BCK0 0 1 0 1 0 1 0 1 0 1 Function 1/1 Dividing (There is a restriction) 1/2 Dividing 1/3 Dividing 1/4 Dividing 1/5 Dividing *** 1/12 Dividing 1/13 Dividing 1/14 Dividing 1/15 Dividing 1/16 Dividing Note) When BCK[3:0]=[0000, MDIV[2:0]=[000] and BCKS="1" settings are prohibited. (ii) BCKG When BCKG="1", MDIV output signal is equally divided into 8 time slots. (iii) BCKS Selecting divided clock signal. BCKS = "0" : LP signal BCKS = "1" : BCKG signal Note) There is a trade-off relationship between voltage booster driving capability and current consumption, so the optimal booster clock shall be decided by your LCD module. Ver.2004-06-29 - 67 - NJU6854 (12-26) Display Control Register : Display TABLE1 [8H] D7 REF D6 SWAP D5 * D4 D3 SHIFT1 SHIFT0 D2 TBC D1 TEN D0 ON/OFF CSb 0 RS 1 RDb 1 WRb 0 (default: REF, SWAP, SHIFT[1:0], TBC, TEN, ON/OFF = 0H, address: 8H) (i) ON/OFF Display Control ON/OFF ON/OFF = "0": Display OFF ON/OFF = "1": Display ON (ii) TEN TEN = "0": Normal TEN = "1": Independent from DDRAM data, pixels are forced to be ON or OFF. (iii) TBC(TEN = "1") TBC = "0" : All pixels ON TBC = "1" : All pixels OFF (iv) SHIFT[1:0] Setting the shift direction of the COM drivers' output. (v) SWAP Switching corresponding relationship between DDRAM data and palette A, B, C. This bit shall be set before DDRAM data writing. SWAP = "0": Normal SWAP = "1": SWAP (vi) REF Reversing the shift direction of SEG drivers' output by redirecting X address. This bit shall be set before DDRAM data writing. REF = "0": Normal REF = "1": Opposite Direction - 68 - Ver.2004-06-29 NJU6854 (12-27) PWM Control Register : PWM TABLE1 [9H] D7 * D6 * D5 D4 D3 D2 D1 D0 PWMC1 PWMC0 PWMB1 PWMB0 PWMA1 PWMA0 CSb 0 RS 1 RDb 1 WRb 0 (default: PWMC[1:0], PWMB[1:0],PWMA[1:0] = 0H, address: 9H) (i) PWMC[1:0], PWMB[1:0], PWMA[1:0] Setting PWM signals for SEGA, SEGB, and SEGC respectively. SEGAi (i=0~131) PWMA1 0 0 1 1 PWMA0 0 1 0 1 Output Timing Forward PWM Backward PWM Forward and Backward alternately Shift Phase SEGBi (i=0~131) PWMB1 0 0 1 1 PWMB0 0 1 0 1 Output Timing Forward PWM Backward PWM Forward and Backward alternately Shift Phase SEGCi (i=0~131) PWMC1 0 0 1 1 PWMC0 0 1 0 1 Output Timing Forward PWM Backward PWM Forward and Backward alternately Shift Phase LP forward backward forward and backward alternatively shift phase M Ver.2004-06-29 - 69 - NJU6854 (12-28) Three Partial Display Areas/ LED Driver Control/REV Bit Register : ECONT TABLE1 [AH] D7 D6 D5 TST0 EN3PTL ENLED D4 REV D3 LED13 D2 D1 LED12 LED11 D0 LED10 CSb 0 RS 1 RDb 1 WRb 0 (default: TST0, EN3PTL, ENLED, REV, LED1[3:0] = 0H, address: AH) (i) TST0 For maker testing, usually set to "0". (ii) EN3PTL When EN3PTL="1", three specified partial areas can be displayed through setting SSC1[7:0]~SSC3[7:0] and PCC1[7:0]~PCC3[7:0]. If setting EN3PTL="0", one or two partial area can be displayed. (iii) ENLED When ENLED="1", data saved at LED1[3:0] can be used to control white LED through control port(LDAT, LSCK, LREQ, LRESB) ENLED = 0 : LDAT, LSCK, LREQ, LRESB ports invalid (high impedance) ENLED = 1 : LDAT, LSCK, LREQ, LRESB ports valid. (iv) LED1 [3:0] When ENLED="1", white LED control ports (LDAT, LSCK, LREQ, LRESB) are valid, LED control signal output from LDAT, LSCK, LREQ and LRESB to LED10, LED11, LED12 and LED13 respectively. Concerning white LED driver, please refer to NJRC white LED controller series (NJU6051/52/53). Besides, the above mentioned bits and ports can be used as general-purpose ports too. Note) For NJRC white LED driver, data pin state will be changed according to request pin. When request pin is "L", data pin of white LED driver is in input state, and when request pin is "H", data pin become output state. when LREQ pin of NJU6854 is "L", LDAT pin output signals, and when LREQ is "H", LDAT is in input state. So, if LDAT, LSCK, LREQ and LRESB are used as common ports, please pay attention to this point. LSCK, LREQ and LRESB pins can be used as 3-bit general-purpose ports too. Example of connection with NJU6053 RSTb REQ NJU6053 SCK DATA LRESB LREQ LSCK LDAT NJU6854 Timing Sequence of data sending LRESb LREQ LSCK LDAT B7 B6 B5 B1 B0 - 70 - Ver.2004-06-29 NJU6854 Timing Sequence of data receiving LRESb LREQ LSCK LDAT B7 B6 B5 B1 B0 Follow Chart of NJU6053 Operation Initialization of NJU6053 (LRESB=L->H) "0"-> LED13 or "1" ->LED13 Data Receiving Request Active (LREQ=H) "1" -> LED12 Data Sending Request Active (LREQ=L) "0"-> LED12 Data Setting(LDAT=DATA(7)) Data(7th bit) -> LED10 Clock Setting (LSCK=L->H) "0" -> LED11 or "1" -> LED11 Data sending Clock Setting (LSCK=L->H) "0" -> LED11 Or "1" -> LED11 Cycle 8 times Clock Setting(LSCK=L->H) "0" ->LED11 Or "1" -> LED11 DATA 6 ~ 1 sent under the same way Data Receiving Data Setting (LDAT=DATA(0)) data(0 bit) -> LED10 Clock Setting (LSCK=L->H) "0" -> LED11 Or "1" -> LED11 EDATA Read In instruction data read, EDATA is read out (v) REV Without changing data in DDRAM, pixel display state can be inverted REV = "0": data="1" pixel ON (Normal) REV = "1": data="0" pixel ON (Reversed) Ver.2004-06-29 - 71 - NJU6854 (12-29) Discharge ON/OFF Register : DIS TABLE1 [BH] D7 * D6 * D5 * D4 * D3 * D2 * D1 DIS2 D0 DIS1 CSb 0 RS 1 RDb 1 WRb 0 (default: DIS[2:1] = 0H, address: BH) (i) DIS1 If DIS1="1", the capacitors connected to V0~V4 pins discharge. DIS1 = "0": Discharge OFF DIS1 = "1": Discharge ON (ii) DIS2 If DIS2="1", the capacitor connected to VOUT pin discharge DIS2 = "0": discharge OFF DIS2 = "1": discharge ON Vout V0 100k(typ) 5M(typ) V1 V2 V3 V4 DIS2 VEE DIS1 V SSH (12-30) LED Driver Data Register : EDATA TABLE1 [CH] D7 D6 LED27 LED26 D5 D4 D3 LED25 LED24 LED23 D2 D1 LED22 LED21 D0 LED20 CSb 0 RS 1 RDb 1 WRb 0 (default: LED2[7:0] = 0H, address: CH) (i)LED2[7:0] Data from NJRC white LED driver(NJU6051/52/53) is saved in this register. (12-31) Instruction Table/Address Register : RA TABLE1 [DH] D7 RSS D6 RA6 D5 RA5 D4 RA4 D3 RA3 D2 RA2 D1 RA1 D0 RA0 CSb 0 RS 1 RDb 1 WRb 0 (default: RA[6:0] = 0H, address: DH) RA[6:4] : Instruction table selection RA6 0 0 0 0 1 1 1 1 RA5 0 0 1 1 0 0 1 1 RA4 0 1 0 1 0 1 0 1 Table indicator 0 1 2 3 4 5 6 7 - 72 - Ver.2004-06-29 NJU6854 RA[3:0] :Register address selection during direct access, or increment number selection in auto increment mode. RA3 RA2 RA1 RA0 Direct access (address selection) 0H 1H 2H 3H 4H 5H 6H 7H *** BH CH DH EH FH Auto increment setting increment number 1 2 3 4 5 6 7 8 *** 12 13 14 15 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 *** 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 RSS: RSS = "1": increment number in auto increment mode. RSS = "0": register address selection for direct access (12-32) Scan Start COM 3 Register : SSC3 TABLE1 [EH] D7 D6 D5 D4 D3 SSC37 SSC36 SSC35 SSC34 SSC33 D2 D1 SSC32 SSC31 D0 SSC30 CSb 0 RS 1 RDb 1 WRb 0 (default: SSC3[7:0] = 0H, address: EH) This instruction sets the logical number of the scan start COM driver for the third partial display, and the setting method just as of the Scan Start COM 1 or 2. This instruction can not be used with normal display and single partial display. When EN3PTL = "1", the setting is valid. Range: SSC2 + PCC2 SSC3 (VPC - 1) (12-33) Line Number of Partial Display 3 Register : PCC3 TABLE1 [FH] D7 D6 D5 D4 D3 D2 D1 D0 PCC37 PCC36 PCC35 PCC34 PCC33 PCC32 PCC31 PCC30 CSb 0 RS 1 RDb 1 WRb 0 (default: PCC3[7:0] = 0H, address: FH) This instruction set line number(DDRAM Y address range) for the third partial display area. In the partial display mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display duty. When EN3PTL = "1", the setting is valid Range: 0 PCC3 (VPC - SSC3) Ver.2004-06-29 - 73 - NJU6854 (12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31) Register : PA0 TABLE2 [0H] D7 * D6 PA06 D5 PA05 D4 PA04 D3 PA03 D2 PA02 D1 PA01 D0 PA00 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA0[6:0] = 0H, Register Address: 0H) Register : PA1 TABLE2 [1H] D7 * D6 PA16 D5 PA15 D4 PA14 D3 PA13 D2 PA12 D1 PA11 D0 PA10 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA1[6:0] = 6H, Register Address: 1H) Register : PA2 TABLE2 [2H] D7 * D6 PA26 D5 PA25 D4 PA24 D3 PA23 D2 PA22 D1 PA21 D0 PA20 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA2[6:0] = AH, Register Address: 2H) Register : PA3 TABLE2 [3H] D7 * D6 PA36 D5 PA35 D4 PA34 D3 PA33 D2 PA32 D1 PA31 D0 PA30 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA3[6:0] = EH, Register Address: 3H) Register : PA4 TABLE2 [4H] D7 * D6 PA46 D5 PA45 D4 PA44 D3 PA43 D2 PA42 D1 PA41 D0 PA40 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA4[6:0] = 12H, Register Address: 4H) Register : PA5 TABLE2 [5H] D7 * D6 PA56 D5 PA55 D4 PA54 D3 PA53 D2 PA52 D1 PA51 D0 PA50 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA5[6:0] = 16H, Register Address: 5H) Register : PA6 TABLE2 [6H] D7 * D6 PA66 D5 PA65 D4 PA64 D3 PA63 D2 PA62 D1 PA61 D0 PA60 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA6[6:0] = 1AH, Register Address: 6H) Register : PA7 TABLE2 [7H] D7 * D6 PA76 D5 PA75 D4 PA74 D3 PA73 D2 PA72 D1 PA71 D0 PA70 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA7[6:0] = 1EH, Register Address: 7H) Register : PA8 TABLE2 [8H] D7 * D6 PA86 D5 PA85 D4 PA84 D3 PA83 D2 PA82 D1 PA81 D0 PA80 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA8[6:0] = 22H, Register Address: 8H) Register : PA9 TABLE2 [9H] D7 * D6 PA96 D5 PA95 D4 PA94 D3 PA93 D2 PA92 D1 PA91 D0 PA90 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA9[6:0] = 26H, Register Address: 9H) Register : PA10 TABLE2 [AH] D7 * D6 PA106 D5 D4 PA105 PA104 D3 PA103 D2 D1 PA102 PA101 D0 PA100 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA10[6:0] = 2AH, Register Address: AH) - 74 - Ver.2004-06-29 NJU6854 Register : PA11 TABLE2 [BH] D7 * D6 PA116 D5 PA115 D4 PA114 D3 PA113 D2 PA112 D1 PA111 D0 PA110 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA11[6:0] = 2EH, Register Address: BH) Register : PA12 TABLE2 [CH] D7 * D6 PA126 D5 D4 PA125 PA124 D3 PA123 D2 D1 PA122 PA121 D0 PA120 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA12[6:0] = 32H, Register Address: CH) Register : PA13 TABLE2 [DH] D7 * D6 PA136 D5 D4 PA135 PA134 D3 PA133 D2 D1 PA132 PA131 D0 PA130 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA13[6:0] = 36H, Register Address: DH) Register : PA14 TABLE2 [EH] D7 * D6 PA146 D5 D4 PA145 PA144 D3 PA143 D2 D1 PA142 PA141 D0 PA140 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA14[6:0] = 3AH, Register Address: EH) Register : PA15 TABLE2 [FH] D7 * D6 PA156 D5 D4 PA155 PA154 D3 PA153 D2 D1 PA152 PA151 D0 PA150 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA15[6:0] = 3EH, Register Address: FH) Register : PA16 TABLE3 [0H] D7 * D6 PA166 D5 D4 PA165 PA164 D3 PA163 D2 D1 PA162 PA161 D0 PA160 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA16[6:0] = 42H, Register Address: 0H) Register : PA17 TABLE3 [1H] D7 * D6 PA176 D5 D4 PA175 PA174 D3 PA173 D2 D1 PA172 PA171 D0 PA170 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA17[6:0] = 46H, Register Address: 1H) Register : PA18 TABLE3 [2H] D7 * D6 PA186 D5 D4 PA185 PA184 D3 PA183 D2 D1 PA182 PA181 D0 PA180 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA18[6:0] = 4AH, Register Address: 2H) Register : PA19 TABLE3 [3H] D7 * D6 PA196 D5 D4 PA195 PA194 D3 PA193 D2 D1 PA192 PA191 D0 PA190 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA19[6:0] = 4EH, Register Address: 3H) Register : PA20 TABLE3 [4H] D7 * D6 PA206 D5 D4 PA205 PA204 D3 PA203 D2 D1 PA202 PA201 D0 PA200 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA20[6:0] = 52H, Register Address: 4H) Register : PA21 TABLE3 [5H] D7 * D6 PA216 D5 D4 PA215 PA214 D3 PA213 D2 D1 PA212 PA211 D0 PA210 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA21[6:0] = 56H, Register Address: 5H) Ver.2004-06-29 - 75 - NJU6854 Register : PA22 TABLE3 [6H] D7 * D6 PA226 D5 D4 PA225 PA224 D3 PA223 D2 D1 PA222 PA221 D0 PA220 CSb 0 RS 1 RDb 1 WRb 0 Register : PA23 TABLE3 [7H] D7 * D6 PA236 (Initialization: PA22[6:0] = 5AH, Register Address: 6H) D5 D4 PA235 PA234 D3 PA233 D2 D1 PA232 PA231 D0 PA230 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA23[6:0] = 5EH, Register Address: 7H) Register : PA24 TABLE3 [8H] D7 * D6 PA246 D5 D4 PA245 PA244 D3 PA243 D2 D1 PA242 PA241 D0 PA240 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA24[6:0] = 62H, Register Address: 8H) Register : PA25 TABLE3 [9H] D7 * D6 PA256 D5 D4 PA255 PA254 D3 PA253 D2 D1 PA252 PA251 D0 PA250 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA25[6:0] = 66H, Register Address: 9H) Register : PA26 TABLE3 [AH] D7 * D6 PA266 D5 D4 PA265 PA264 D3 PA263 D2 D1 PA262 PA261 D0 PA260 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA26[6:0] = 6AH, Register Address: AH) Register : PA27 TABLE3 [BH] D7 * D6 PA276 D5 D4 PA275 PA274 D3 PA273 D2 D1 PA272 PA271 D0 PA270 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA27[6:0] = 6EH, Register Address: BH) Register : PA28 TABLE3 [CH] D7 * D6 PA286 D5 D4 PA285 PA284 D3 PA283 D2 D1 PA282 PA281 D0 PA280 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA28[6:0] = 72H, Register Address: CH) Register : PA29 TABLE3 [DH] D7 * D6 PA296 D5 D4 PA295 PA294 D3 PA293 D2 D1 PA292 PA291 D0 PA290 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA29[6:0] = 76H, Register Address: DH) Register : PA30 TABLE3 [EH] D7 * D6 PA306 D5 D4 PA305 PA304 D3 PA303 D2 D1 PA302 PA301 D0 PA300 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA30[6:0] = 7AH, Register Address: EH) Register : PA31 TABLE3 [FH] D7 * D6 PA316 D5 D4 PA315 PA314 D3 PA313 D2 D1 PA312 PA311 D0 PA310 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PA31[6:0] = 7FH, Register Address: FH) Register : PB0 TABLE4 [0H] D7 * D6 PB06 D5 PB05 D4 PB04 D3 PB03 D2 PB02 D1 PB01 D0 PB00 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB0[6:0] = 0H, Register Address: 0H) - 76 - Ver.2004-06-29 NJU6854 Register : PB1 TABLE4 [1H] D7 * D6 PB16 D5 PB15 D4 PB14 D3 PB13 D2 PB12 D1 PB11 D0 PB10 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB1[6:0] = 6H, Register Address: 1H) Register : PB2 TABLE4 [2H] D7 * D6 PB26 D5 PB25 D4 PB24 D3 PB23 D2 PB22 D1 PB21 D0 PB20 CSb 0 RS 1 RDb 1 WRb 0 Register : PB3 TABLE4 [3H] D7 * D6 PB36 D5 PB35 (Initialization: PB2[6:0] = AH, Register Address: 2H) D4 PB34 D3 PB33 D2 PB32 D1 PB31 D0 PB30 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB3[6:0] = EH, Register Address: 3H) Register : PB4 TABLE4 [4H] D7 * D6 PB46 D5 PB45 D4 PB44 D3 PB43 D2 PB42 D1 PB41 D0 PB40 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB4[6:0] = 12H, Register Address: 4H) Register : PB5 TABLE4 [5H] D7 * D6 PB56 D5 PB55 D4 PB54 D3 PB53 D2 PB52 D1 PB51 D0 PB50 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB5[6:0] = 16H, Register Address: 5H) Register : PB6 TABLE4 [6H] D7 * D6 PB66 D5 PB65 D4 PB64 D3 PB63 D2 PB62 D1 PB61 D0 PB60 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB6[6:0] = 1AH, Register Address: 6H) Register : PB7 TABLE4 [7H] D7 * D6 PB76 D5 PB75 D4 PB74 D3 PB73 D2 PB72 D1 PB71 D0 PB70 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB7[6:0] = 1EH, Register Address: 7H) Register : PB8 TABLE4 [8H] D7 * D6 PB86 D5 PB85 D4 PB84 D3 PB83 D2 PB82 D1 PB81 D0 PB80 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB8[6:0] = 22H, Register Address: 8H) Register : PB9 TABLE4 [9H] D7 * D6 PB96 D5 PB95 D4 PB94 D3 PB93 D2 PB92 D1 PB91 D0 PB90 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB9[6:0] = 26H, Register Address: 9H) Register : PB10 TABLE4 [AH] D7 * D6 PB106 D5 D4 D3 PB105 PB104 PB103 D2 D1 PB102 PB101 D0 PB100 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB10[6:0] = 2AH, Register Address: AH) Register : PB11 TABLE4 [BH] D7 * D6 PB116 D5 D4 PB115 PB114 D3 PB113 D2 D1 PB112 PB111 D0 PB110 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB11[6:0] = 2EH, Register Address: BH) Register : PB12 TABLE4 [CH] D7 * D6 PB126 D5 D4 D3 PB125 PB124 PB123 D2 D1 PB122 PB121 D0 PB120 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB12[6:0] = 32H, Register Address: CH) Ver.2004-06-29 - 77 - NJU6854 Register : PB13 TABLE4 [DH] D7 * D6 PB136 D5 D4 D3 PB135 PB134 PB133 D2 D1 PB132 PB131 D0 PB130 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB13[6:0] = 36H, Register Address: DH) Register : PB14 TABLE4 [EH] D7 * D6 PB146 D5 D4 D3 PB145 PB144 PB143 D2 D1 PB142 PB141 D0 PB140 CSb 0 RS 1 RDb 1 WRb 0 Register : PB15 TABLE4 [FH] D7 * D6 PB156 (Initialization: PB14[6:0] = 3AH, Register Address: EH) D5 D4 D3 PB155 PB154 PB153 D2 D1 PB152 PB151 D0 PB150 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB15[6:0] = 3EH, Register Address: FH) Register : PB16 TABLE5 [0H] D7 * D6 PB166 D5 D4 D3 PB165 PB164 PB163 D2 D1 PB162 PB161 D0 PB160 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB16[6:0] = 42H, Register Address: 0H) Register : PB17 TABLE5 [1H] D7 * D6 PB176 D5 D4 D3 PB175 PB174 PB173 D2 D1 PB172 PB171 D0 PB170 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB17[6:0] = 46H, Register Address: 1H) Register : PB18 TABLE5 [2H] D7 * D6 PB186 D5 D4 D3 PB185 PB184 PB183 D2 D1 PB182 PB181 D0 PB180 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB18[6:0] = 4AH, Register Address: 2H) Register : PB19 TABLE5 [3H] D7 * D6 PB196 D5 D4 D3 PB195 PB194 PB193 D2 D1 PB192 PB191 D0 PB190 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB19[6:0] = 4EH, Register Address: 3H) Register : PB20 TABLE5 [4H] D7 * D6 PB206 D5 D4 D3 PB205 PB204 PB203 D2 D1 PB202 PB201 D0 PB200 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB20[6:0] = 52H, Register Address: 4H) Register : PB21 TABLE5 [5H] D7 * D6 PB216 D5 D4 D3 PB215 PB214 PB213 D2 D1 PB212 PB211 D0 PB210 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB21[6:0] = 56H, Register Address: 5H) Register : PB22 TABLE5 [6H] D7 * D6 PB226 D5 D4 D3 PB225 PB224 PB223 D2 D1 PB222 PB221 D0 PB220 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB22[6:0] = 5AH, Register Address: 6H) Register : PB23 TABLE5 [7H] D7 * D6 PB236 D5 D4 D3 PB235 PB234 PB233 D2 D1 PB232 PB231 D0 PB230 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB23[6:0] = 5EH, Register Address: 7H) - 78 - Ver.2004-06-29 NJU6854 Register : PB24 TABLE5 [8H] D7 * D6 PB246 D5 D4 D3 PB245 PB244 PB243 D2 D1 PB242 PB241 D0 PB240 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB24[6:0] = 62H, Register Address: 8H) Register : PB25 TABLE5 [9H] D7 * D6 PB256 D5 D4 D3 PB255 PB254 PB253 D2 D1 PB252 PB251 D0 PB250 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB25[6:0] = 66H, Register Address: 9H) Register : PB26 TABLE5 [AH] D7 * D6 PB266 D5 D4 D3 PB265 PB264 PB263 D2 D1 PB262 PB261 D0 PB260 CSb 0 RS 1 RDb 1 WRb 0 Register : PB27 TABLE5 [BH] D7 * D6 PB276 (Initialization: PB26[6:0] = 6AH, Register Address: AH) D5 D4 D3 PB275 PB274 PB273 D2 D1 PB272 PB271 D0 PB270 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB27[6:0] = 6EH, Register Address: BH) Register : PB28 TABLE5 [CH] D7 * D6 PB286 D5 D4 D3 PB285 PB284 PB283 D2 D1 PB282 PB281 D0 PB280 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB28[6:0] = 72H, Register Address: CH) Register : PB29 TABLE5 [DH] D7 * D6 PB296 D5 D4 D3 PB295 PB294 PB293 D2 D1 PB292 PB291 D0 PB290 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB29[6:0] = 76H, Register Address: DH) Register : PB30 TABLE5 [EH] D7 * D6 PB306 D5 D4 D3 PB305 PB304 PB303 D2 D1 PB302 PB301 D0 PB300 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB30[6:0] = 7AH, Register Address: EH) Register : PB31 TABLE5 [FH] D7 * D6 PB316 D5 D4 D3 PB315 PB314 PB313 D2 D1 PB312 PB311 D0 PB310 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PB31[6:0] = 7FH, Register Address: FH) Register : PC0 TABLE6 [0H] D7 * D6 PC06 D5 PC05 D4 PC04 D3 PC03 D2 PC02 D1 PC01 D0 PC00 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC0[6:0] = 0H, Register Address: 0H) Register : PC1 TABLE6 [1H] D7 * D6 PC16 D5 PC15 D4 PC14 D3 PC13 D2 PC12 D1 PC11 D0 PC10 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC1[6:0] = 6H, Register Address: 1H) Register : PC2 TABLE6 [2H] D7 * D6 PC26 D5 PC25 D4 PC24 D3 PC23 D2 PC22 D1 PC21 D0 PC20 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC2[6:0] = AH, Register Address: 2H) Ver.2004-06-29 - 79 - NJU6854 Register : PC3 TABLE6 [3H] D7 * D6 PC36 D5 PC35 D4 PC34 D3 PC33 D2 PC32 D1 PC31 D0 PC30 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC3[6:0] = EH, Register Address: 3H) Register : PC4 TABLE6 [4H] D7 * D6 PC46 D5 PC45 D4 PC44 D3 PC43 D2 PC42 D1 PC41 D0 PC40 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC4[6:0] = 12H, Register Address: 4H) Register : PC5 TABLE6 [5H] D7 * D6 PC56 D5 PC55 D4 PC54 D3 PC53 D2 PC52 D1 PC51 D0 PC50 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC5[6:0] = 16H, Register Address: 5H) Register : PC6 TABLE6 [6H] D7 * D6 PC66 D5 PC65 D4 PC64 D3 PC63 D2 PC62 D1 PC61 D0 PC60 CSb 0 RS 1 RDb 1 WRb 0 Register : PC7 TABLE6 [7H] D7 * D6 PC76 D5 PC75 (Initialization: PC6[6:0] = 1AH, Register Address: 6H) D4 PC74 D3 PC73 D2 PC72 D1 PC71 D0 PC70 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC7[6:0] = 1EH, Register Address: 7H) Register : PC8 TABLE6 [8H] D7 * D6 PC86 D5 PC85 D4 PC84 D3 PC83 D2 PC82 D1 PC81 D0 PC80 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC8[6:0] = 22H, Register Address: 8H) Register : PC9 TABLE6 [9H] D7 * D6 PC96 D5 PC95 D4 PC94 D3 PC93 D2 PC92 D1 PC91 D0 PC90 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC9[6:0] = 26H, Register Address: 9H) Register : PC10 TABLE6 [AH] D7 * D6 PC106 D5 D4 D3 PC105 PC104 PC103 D2 D1 PC102 PC101 D0 PC100 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC10[6:0] = 2AH, Register Address: AH) Register : PC11 TABLE6 [BH] D7 * D6 PC116 D5 D4 D3 PC115 PC114 PC113 D2 D1 PC112 PC111 D0 PC110 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC11[6:0] = 2EH, Register Address: BH) Register : PC12 TABLE6 [CH] D7 * D6 PC126 D5 D4 D3 PC125 PC124 PC123 D2 D1 PC122 PC121 D0 PC120 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC12[6:0] = 32H, Register Address: CH) Register : PC13 TABLE6 [DH] D7 * D6 PC136 D5 D4 D3 PC135 PC134 PC133 D2 D1 PC132 PC131 D0 PC130 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC13[6:0] = 36H, Register Address: DH) Register : PC14 TABLE6 [EH] D7 * D6 PC146 D5 D4 D3 PC145 PC144 PC143 D2 D1 PC142 PC141 D0 PC140 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC14[6:0] = 3AH, Register Address: EH) - 80 - Ver.2004-06-29 NJU6854 Register : PC15 TABLE6 [FH] D7 * D6 PC156 D5 D4 D3 PC155 PC154 PC153 D2 D1 PC152 PC151 D0 PC150 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC15[6:0] = 3EH, Register Address: FH) Register : PC16 TABLE7 [0H] D7 * D6 PC166 D5 D4 D3 PC165 PC164 PC163 D2 D1 PC162 PC161 D0 PC160 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC16[6:0] = 42H, Register Address: 0H) Register : PC17 TABLE7 [1H] D7 * D6 PC176 D5 D4 D3 PC175 PC174 PC173 D2 D1 PC172 PC171 D0 PC170 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC17[6:0] = 46H, Register Address: 1H) Register : PC18 TABLE7 [2H] D7 * D6 PC186 D5 D4 D3 PC185 PC184 PC183 D2 D1 PC182 PC181 D0 PC180 CSb 0 RS 1 RDb 1 WRb 0 Register : PC19 TABLE7 [3H] D7 * D6 PC196 (Initialization: PC18[6:0] = 4AH, Register Address: 2H) D5 D4 D3 PC195 PC194 PC193 D2 D1 PC192 PC191 D0 PC190 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC19[6:0] = 4EH, Register Address: 3H) Register : PC20 TABLE7 [4H] D7 * D6 PC206 D5 D4 D3 PC205 PC204 PC203 D2 D1 PC202 PC201 D0 PC200 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC20[6:0] = 52H, Register Address: 4H) Register : PC21 TABLE7 [5H] D7 * D6 PC216 D5 D4 D3 PC215 PC214 PC213 D2 D1 PC212 PC211 D0 PC210 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC21[6:0] = 56H, Register Address: 5H) Register : PC22 TABLE7 [6H] D7 * D6 PC226 D5 D4 D3 PC225 PC224 PC223 D2 D1 PC222 PC221 D0 PC220 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC22[6:0] = 5AH, Register Address: 6H) Register : PC23 TABLE7 [7H] D7 * D6 PC236 D5 D4 D3 PC235 PC234 PC233 D2 D1 PC232 PC231 D0 PC230 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC23[6:0] = 5EH, Register Address: 7H) Register : PC24 TABLE7 [8H] D7 * D6 PC246 D5 D4 D3 PC245 PC244 PC243 D2 D1 PC242 PC241 D0 PC240 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC24[6:0] = 62H, Register Address: 8H) Register : PC25 TABLE7 [9H] D7 * D6 PC256 D5 D4 D3 PC255 PC254 PC253 D2 D1 PC252 PC251 D0 PC250 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC25[6:0] = 66H, Register Address: 9H) Ver.2004-06-29 - 81 - NJU6854 Register : PC26 TABLE7 [AH] D7 * D6 PC266 D5 D4 D3 PC265 PC264 PC263 D2 D1 PC262 PC261 D0 PC260 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC26[6:0] = 6AH, Register Address: AH) Register : PC27 TABLE7 [BH] D7 * D6 PC276 D5 D4 D3 PC275 PC274 PC273 D2 D1 PC272 PC271 D0 PC270 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC27[6:0] = 6EH, Register Address: BH) Register : PC28 TABLE7 [CH] D7 * D6 PC286 D5 D4 D3 PC285 PC284 PC283 D2 D1 PC282 PC281 D0 PC280 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC28[6:0] = 72H, Register Address: CH) Register : PC29 TABLE7 [DH] D7 * D6 PC296 D5 D4 D3 PC295 PC294 PC293 D2 D1 PC292 PC291 D0 PC290 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC29[6:0] = 76H, Register Address: DH) Register : PC30 TABLE7 [EH] D7 * D6 PC306 D5 D4 D3 PC305 PC304 PC303 D2 D1 PC302 PC301 D0 PC300 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC30[6:0] = 7AH, Register Address: EH) Register : PC31 TABLE8 [FH] D7 * D6 PC316 D5 D4 D3 PC315 PC314 PC313 D2 D1 PC312 PC311 D0 PC310 CSb 0 RS 1 RDb 1 WRb 0 (Initialization: PC31[6:0] = 7FH, Register Address: FH) - 82 - Ver.2004-06-29 NJU6854 65k-color Mode(32 Grayscale from 128 Levels, PWM1=1, PWM0=1) [Three groups of palettes Aj, Bj and Cj (j=0~31) are available] Palette 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 Grayscale level 0/127 1/127 2/127 3/127 4/127 5/127 6/127 7/127 8/127 9/127 10/127 11/127 12/127 13/127 14/127 15/127 16/127 17/127 18/127 19/127 20/127 21/127 22/127 23/127 24/127 25/127 26/127 27/127 28/127 29/127 30/127 31/127 32/127 33/127 34/127 35/127 36/127 37/127 38/127 39/127 40/127 41/127 42/127 43/127 44/127 45/127 46/127 47/127 48/127 49/127 50/127 51/127 52/127 53/127 54/127 55/127 56/127 57/127 58/127 59/127 60/127 61/127 62/127 63/127 Remarks(2) Palette 0 initial value[6:0] (marking points are default positions) Palette Grayscale level 1000000 64/127 1000001 65/127 1000010 66/127 1000011 67/127 1000100 68/127 1000101 69/127 1000110 70/127 1000111 71/127 1001000 72/127 1001001 73/127 1001010 74/127 1001011 75/127 1001100 76/127 1001101 77/127 1001110 78/127 1001111 79/127 1010000 80/127 1010001 81/127 1010010 82/127 1010011 83/127 1010100 84/127 1010101 85/127 1010110 86/127 1010111 87/127 1011000 88/127 1011001 89/127 1011010 90/127 1011011 91/127 1011100 92/127 1011101 93/127 1011110 94/127 1011111 95/127 1100000 96/127 1100001 97/127 1100010 98/127 1100011 99/127 1100100 100/127 1100101 101/127 1100110 102/127 1100111 103/127 1101000 104/127 1101001 105/127 1101010 106/127 1101011 107/127 1101100 108/127 1101101 109/127 1101110 110/127 1101111 111/127 1110000 112/127 1110001 113/127 1110010 114/127 1110011 115/127 1110100 116/127 1110101 117/127 1110110 118/127 1110111 119/127 1111000 120/127 1111001 121/127 1111010 122/127 1111011 123/127 1111100 124/127 1111101 125/127 1111110 126/127 1111111 127/127 Remarks(2) Palette 16 initial value[6:0] Palette X initial value [6:0](1) Palette 1 initial value[6:0] Palette 17 initial value[6:0] Palette 2 initial value[6:0] Palette 18 initial value[6:0] Palette 3 initial value[6:0] Palette 19 initial value[6:0] Palette 4 initial value[6:0] Palette 20 initial value[6:0] Palette 5 initial value[6:0] Palette 21 initial value[6:0] Palette 6 initial value[6:0] Palette 22 initial value[6:0] Palette 7 initial value[6:0] Palette 23 initial value[6:0] Palette 8 initial value[6:0] Palette 24 initial value[6:0] Palette 9 initial value[6:0] Palette 25 initial value[6:0] Palette 10 initial value[6:0] Palette 26 initial value[6:0] Palette 11 initial value[6:0] Palette 27 initial value[6:0] Palette 12 initial value[6:0] Palette 28 initial value[6:0] Palette 13 initial value[6:0] Palette 29 initial value[6:0] Palette 14 initial value[6:0] Palette 30 initial value[6:0] Palette 15 initial value[6:0] Palette 31 initial value[6:0] Remark 1) PBX[6:0] grayscale palette is enable under GS = `0'(defaults) setting. Remark 2) Please refer to the description of setting range, effective bit and rule for each grayscale palettes Ver.2004-06-29 - 83 - NJU6854 65k-color Mode(32 Grayscale from 64 Levels, PWM1=0, PWM0=0) (marking points are default positions) [Three groups of palettes Aj, Bj and Cj (j=0~31) are available] Palette 000000X 000001X 000010X 000011X 000100X 000101X 000110X 000111X 001000X 001001X 001010X 001011X 001100X 001101X 001110X 001111X 010000X 010001X 010010X 010011X 010100X 010101X 010110X 010111X 011000X 011001X 011010X 011011X 011100X 011101X 011110X 011111X Grayscale level 0/63 1/63 2/63 3/63 4/63 5/63 6/63 7/63 8/63 9/63 10/63 11/63 12/63 13/63 14/63 15/63 16/63 17/63 18/63 19/63 20/63 21/63 22/63 23/63 24/63 25/63 26/63 27/63 28/63 29/63 30/63 31/63 Remarks Palette 0 initial value[6:1] Palette X initial value[6:1] Palette 1 initial value[6:1] Palette 2 initial value[6:1] Palette 3 initial value[6:1] Palette 4 initial value[6:1] Palette 5 initial value[6:1] Palette 6 initial value[6:1] Palette 7 initial value[6:1] Palette 8 initial value[6:1] Palette 9 initial value[6:1] Palette 10 initial value[6:1] Palette 11 initial value[6:1] Palette 12 initial value[6:1] Palette 13 initial value[6:1] Palette 14 initial value[6:1] Palette 15 initial value[6:1] Palette 100000X 100001X 100010X 100011X 100100X 100101X 100110X 100111X 101000X 101001X 101010X 101011X 101100X 101101X 101110X 101111X 110000X 110001X 110010X 110011X 110100X 110101X 110110X 110111X 111000X 111001X 111010X 111011X 111100X 111101X 111110X 111111X Grayscale level 32/63 33/63 34/63 35/63 36/63 37/63 38/63 39/63 40/63 41/63 42/63 43/63 44/63 45/63 46/63 47/63 48/63 49/63 50/63 51/63 52/63 53/63 54/63 55/63 56/63 57/63 58/63 59/63 60/63 61/63 62/63 63/63 Remarks Palette 16 initial value[6:1] Palette 17 initial value[6:1] Palette 18 initial value[6:1] Palette 19 initial value[6:1] Palette 20 initial value[6:1] Palette 21 initial value[6:1] Palette 22 initial value[6:1] Palette 23 initial value[6:1] Palette 24 initial value[6:1] Palette 25 initial value[6:1] Palette 26 initial value[6:1] Palette 27 initial value[6:1] Palette 28 initial value][6:1] Palette 29 initial value[6:1] Palette 30 initial value[6:1] Palette 31 initial value[6:1] 65k-color Mode(32 Grayscale from 32 Levels, PWM1=0, PWM0=1) [Three groups of palettes Aj, Bj and Cj (j=0~31) are available] (marking points are default positions) Palette 00000XX 00001XX 00010XX 00011XX 00100XX 00101XX 00110XX 00111XX 01000XX 01001XX 01010XX 01011XX 01100XX 01101XX 01110XX 01111XX Grayscale level 0/31 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks Palette 0/X initial value[6:2] Palette 1 initial value[6:2] Palette 2 initial value[6:2] Palette 3 initial value[6:2] Palette 4 initial value[6:2] Palette 5 initial value[6:2] Palette 6 initial value[6:2] Palette 7 initial value[6:2] Palette 8 initial value[6:2] Palette 9 initial value[6:2] Palette 10 initial value[6:2] Palette 11 initial value[6:2] Palette 12 initial value[6:2] Palette 13 initial value[6:2] Palette 14 initial value[6:2] Palette 15 initial value[6:2] Palette 10000XX 10001XX 10010XX 10011XX 10100XX 10101XX 10110XX 10111XX 11000XX 11001XX 11010XX 11011XX 11100XX 11101XX 11110XX 11111XX Grayscale level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks Palette 16 initial value[6:2] Palette 17 initial value[6:2] Palette 18 initial value[6:2] Palette 19 initial value[6:2] Palette 20 initial value[6:2] Palette 21 initial value[6:2] Palette 22 initial value[6:2] Palette 23 initial value[6:2] Palette 24 initial value[6:2] Palette 25 initial value[6:2] Palette 26 initial value[6:2] Palette 27 initial value[6:2] Palette 28 initial value][6:2] Palette 29 initial value[6:2] Palette 30 initial value[6:2] Palette 31 initial value[6:2] - 84 - Ver.2004-06-29 NJU6854 4k-color Mode(16 Grayscale from 128 Levels, PWM1=1, PWM0=1) Only odd number palettes ( ex palette1 palette3 .. palette31)are effective under 4k color mode. [Three groups of palettes Aj, Bj and Cj (j=1,3,5 ...29, 31) are available] (marking points are default positions) Palette 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 Grayscale level 0/127 1/127 2/127 3/127 4/127 5/127 6/127 7/127 8/127 9/127 10/127 11/127 12/127 13/127 14/127 15/127 16/127 17/127 18/127 19/127 20/127 21/127 22/127 23/127 24/127 25/127 26/127 27/127 28/127 29/127 30/127 31/127 32/127 33/127 34/127 35/127 36/127 37/127 38/127 39/127 40/127 41/127 42/127 43/127 44/127 45/127 46/127 47/127 48/127 49/127 50/127 51/127 52/127 53/127 54/127 55/127 56/127 57/127 58/127 59/127 60/127 61/127 62/127 63/127 Remarks Palette 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 Grayscale level 64/127 65/127 66/127 67/127 68/127 69/127 70/127 71/127 72/127 73/127 74/127 75/127 76/127 77/127 78/127 79/127 80/127 81/127 82/127 83/127 84/127 85/127 86/127 87/127 88/127 89/127 90/127 91/127 92/127 93/127 94/127 95/127 96/127 97/127 98/127 99/127 100/127 101/127 102/127 103/127 104/127 105/127 106/127 107/127 108/127 109/127 110/127 111/127 112/127 113/127 114/127 115/127 116/127 117/127 118/127 119/127 120/127 121/127 122/127 123/127 124/127 125/127 126/127 127/127 Remarks Palette 1 initial value[6:0] Palette 17 initial value[6:0] Palette 3 initial value[6:0] Palette 19 initial value[6:0] Palette 5 initial value[6:0] Palette 21 initial value[6:0] Palette 7 initial value[6:0] Palette 23 initial value[6:0] Palette 9 initial value[6:0] Palette 25 initial value[6:0] Palette 11 initial value[6:0] Palette 27 initial value[6:0] Palette 13 initial value[6:0] Palette 29 initial value[6:0] Palette 15 initial value[6:0] Palette 31 initial value[6:0] Ver.2004-06-29 - 85 - NJU6854 4k-color Mode(16 Grayscale from 64 Levels, PWM1=0, PWM0=0) [Three groups of palettes Aj, Bj and Cj (j=1,3,5 ...29, 31) are available] Palette 000000X 000001X 000010X 000011X 000100X 000101X 000110X 000111X 001000X 001001X 001010X 001011X 001100X 001101X 001110X 001111X 010000X 010001X 010010X 010011X 010100X 010101X 010110X 010111X 011000X 011001X 011010X 011011X 011100X 011101X 011110X 011111X Grayscale level 0/63 1/63 2/63 3/63 4/63 5/63 6/63 7/63 8/63 9/63 10/63 11/63 12/63 13/63 14/63 15/63 16/63 17/63 18/63 19/63 20/63 21/63 22/63 23/63 24/63 25/63 26/63 27/63 28/63 29/63 30/63 31/63 Remarks Palette 100000X 100001X 100010X 100011X 100100X 100101X 100110X 100111X 101000X 101001X 101010X 101011X 101100X 101101X 101110X 101111X 110000X 110001X 110010X 110011X 110100X 110101X 110110X 110111X 111000X 111001X 111010X 111011X 111100X 111101X 111110X 111111X (marking points are default positions) Grayscale level Remarks 32/63 33/63 34/63 35/63 Palette 17 initial value[6:1] 36/63 37/63 38/63 39/63 Palette 19 initial value[6:1] 40/63 41/63 42/63 43/63 Palette 21 initial value[6:1] 44/63 45/63 46/63 47/63 Palette 23 initial value[6:1] 48/63 49/63 50/63 51/63 Palette 25 initial value[6:1] 52/63 53/63 54/63 55/63 Palette 27 initial value[6:1] 56/63 57/63 58/63 59/63 Palette 29 initial value[6:1] 60/63 61/63 62/63 63/63 Palette 31 initial value[6:1] Palette 1 initial value[6:1] Palette 3 initial value[6:1] Palette 5 initial value[6:1] Palette 7 initial value[6:1] Palette 9 initial value[6:1] Palette 11 initial value[6:1] Palette 13 initial value[6:1] Palette 15 initial value[6:1] 4k-color Mode(16 Grayscale from 32 Levels, PWM1=0, PWM0=1) [Three groups of palettes Aj, Bj and Cj (j=1,3,5 ...29, 31) are available] (marking points are default positions) Palette 00000XX 00001XX 00010XX 00011XX 00100XX 00101XX 00110XX 00111XX 01000XX 01001XX 01010XX 01011XX 01100XX 01101XX 01110XX 01111XX Grayscale level 0/31 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks Palette 1 initial value[6:2] Palette 3 initial value[6:2] Palette 5 initial value[6:2] Palette 7 initial value[6:2] Palette 9 initial value[6:2] Palette 11 initial value[6:2] Palette 13 initial value[6:2] Palette 15 initial value[6:2] Palette 10000XX 10001XX 10010XX 10011XX 10100XX 10101XX 10110XX 10111XX 11000XX 11001XX 11010XX 11011XX 11100XX 11101XX 11110XX 11111XX Grayscale level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks Palette 17 initial value[6:2] Palette 19 initial value[6:2] Palette 21 initial value[6:2] Palette 23 initial value[6:2] Palette 25 initial value[6:2] Palette 27 initial value[6:2] Palette 29 initial value[6:2] Palette 31 initial value[6:2] 4k-color Mode(16 Grayscale from 16 Levels, PWM1=1, PWM0=0) [Three groups of palettes Aj, Bj and Cj (j=1,3,5 ...29, 31) are available] (marking points are default positions) Palette 0000XXX 0001XXX 0010XXX 0011XXX 0100XXX 0101XXX 0110XXX 0111XXX Grayscale level 0/15 1/15 2/15 3/15 4/15 5/15 6/15 7/15 Remarks Palette 1 initial value[6:3] Palette 3 initial value[6:3] Palette 5 initial value[6:3] Palette 7 initial value[6:3] Palette 9 initial value[6:3] Palette 11 initial value[6:3] Palette 13 initial value[6:3] Palette 15 initial value[6:3] Palette 1000XXX 1001XXX 1010XXX 1011XXX 1100XXX 1101XXX 1110XXX 1111XXX Grayscale level 8/15 9/15 10/15 11/15 12/15 13/15 14/15 15/15 Remarks Palette 17 initial value[6:3] Palette 19 initial value[6:3] Palette 21 initial value[6:3] Palette 23 initial value[6:3] Palette 25 initial value[6:3] Palette 27 initial value[6:3] Palette 29 initial value[6:3] Palette 31 initial value[6:3] - 86 - Ver.2004-06-29 NJU6854 The setting range of the palette level which can be set up is limited in each palette (RGB common). level Hex Dec 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A 10 B 11 C 12 D 13 E 14 F 15 10 16 11 17 12 18 13 19 14 20 15 21 16 22 17 23 18 24 19 25 1A 26 1B 27 1C 28 1D 29 1E 30 1F 31 20 32 21 33 22 34 23 35 24 36 25 37 26 38 27 39 28 40 29 41 2A 42 2B 43 2C 44 2D 45 2E 46 2F 47 30 48 31 49 32 50 33 51 34 52 35 53 36 54 37 55 38 56 39 57 3A 58 3B 59 3C 60 3D 61 3E 62 3F 63 40 64 41 65 42 66 43 67 44 68 45 69 46 70 47 71 48 72 49 73 4A 74 4B 75 4C 76 4D 77 4E 78 4F 79 50 80 51 81 52 82 53 83 54 84 55 85 56 86 57 87 58 88 59 89 5A 90 5B 91 5C 92 5D 93 5E 94 5F 95 60 96 61 97 62 98 63 99 64 100 65 101 66 102 67 103 68 104 69 105 6A 106 6B 107 6C 108 6D 109 6E 110 6F 111 70 112 71 113 72 114 73 115 74 116 75 117 76 118 77 119 78 120 79 121 7A 122 7B 123 7C 124 7D 125 7E 126 7F 127 P6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette register P4 P3 P2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X 1 2 3 4 5 6 7 8 9 10 11 12 13 Palette selection range 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Caution: Do not set same level for each grayscale palette ( palettem = paletten , m = 0~31, n = 0~31) Forbidden random level palette ( paletten > paletten+1) Ver.2004-06-29 - 87 - NJU6854 The setting range of the palette level can be expressed as the following table. Palette No. 0 X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Palette register MSB 6 5 0 0 4 3 2 Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Except(0,0) Except(0,0) Except(0,0) Except(0,0) Except(0,0) Except(0,0) Except(0,0) Except(0,0) 1 1 1 1 1 1 1 1 Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything Anything 1 LSB 0 0 0 0 Except(1,1) Except(1,1) Except(1,1) Except(1,1) Caution: (1) Do not set the same grayscale level in each grayscale palette(forbidden case: palettem = palettem+n , m=0~31 n=0~31) (2) Do not set the zigzag typed grayscale palette. (forbidden case: paletten > paletten+1, n=0~31 ) - 88 - Ver.2004-06-29 NJU6854 (13) PARTIAL DISPLAY FUNCTION Partial display function is used to save power. In the partial display mode, only specified common drivers output scanning signals, therefore part of the panel area is selected for display. Because the duty ratio and LCD driving voltage are lowed in partial display mode. Current consumption can be minimized. NJU6854 can realize 3 partial display areas on the screen once. The setting of Partial display function is conducted through Scan Start COM 1~3(SSC1~3) registers, Partial Display Line Number 1~3(PCC1~3) registers, Power Control 1~2 (TCBI,POW2) registers, Amplifier Gain/Booster Level(GVU) register, and 3 Partial Display/LED Control/Rev (ECONT) register. Refer to (15)TYPICAL INSTRUCTION SEQUENCES for the functions setting The image of partial display. (i) Full Screen Display SSC1 (Scan Start COM1) VPC(Display line number) (ii) Partial Display (1 area) VPC(Display line number) SSC1 (Scan Start COM1) PCC1(partial display line number 1) (iii) Partial Display (2 areas) VPC(Display line number) SSC1 (Scan Start COM1) SSC2 (Scan Start COM 2) (iv) Partial Display (3 areas) SSC1 (Scan Start COM1) SSC2 (Scan Start COM 2) SSC3 (Scan Start COM 3) VPC(Display line number) PCC1(partial display line number 1) PCC2(partial display line number 2) PCC3(partial display line number 3) PCC1(partial display line number 1) PCC2(partial display line number 2) Note) For the full screen display, set the Scan Start COM 1(SCC1) and the Display Line Number(VPC). For the partial display, set the Scan Start COM 1~3(SCC1~3) and the Partial Display Line Number 1~3(PCC1~3). In this case, the Partial Display Line Number 1~3(PCC1~3) have priority over the Display Line Number(VPC), and thus the display duty is: Duty=PCC1+PCC2+PCC. Ver.2004-06-29 - 89 - NJU6854 (14) RELATIONSHIP BETWEEN LOGICAL COM NUMBER AND PHYSICAL COMMON DRIVER (EN3PTL='0') VPC (Display line number) HCT (Header COM) SHIFT[1] (COM shift A/B set) SHIFT[0] (COM shift direction) SSC1 (Scan Start COM 1) SSC2 (Scan Start COM 2) PCC1 (Line No. of partial display 1) PCC2 (Line No. of partial display 2) SSC3 (Scan Start COM 3) PCC3 (Line No. of partial display 3) A COMA0 COMA1 COMA2 COMA3 COMA4 COMA5 COMA6 COMA7 COMA8 COMA9 COMA10 COMA11 COMA12 COMA13 COMA14 COMA15 COMA16 COMA17 COMA18 COMA19 COMA20 COMA21 COMA22 COMA23 COMA24 COMA25 COMA26 COMA27 COMA28 COMA29 COMA30 COMA31 COMA32 COMA33 COMA34 COMA35 COMA36 COMA37 COMA38 COMA39 COMA40 COMA41 COMA42 COMA43 COMA44 COMA45 COMA46 COMA47 COMA48 COMA49 COMA50 COMA51 COMA52 COMA53 COMA54 COMA55 COMA56 COMA57 COMA58 COMA59 COMA60 COMA61 COMA62 COMA63 COMA64 COMA65 REMARK B COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 COMB8 COMB9 COMB10 COMB11 COMB12 COMB13 COMB14 COMB15 COMB16 COMB17 COMB18 COMB19 COMB20 COMB21 COMB22 COMB23 COMB24 COMB25 COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB33 COMB34 COMB35 COMB36 COMB37 COMB38 COMB39 COMB40 COMB41 COMB42 COMB43 COMB44 COMB45 COMB46 COMB47 COMB48 COMB49 COMB50 COMB51 COMB52 COMB53 COMB54 COMB55 COMB56 COMB57 COMB58 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 106 13 `0' (A start-> A end -> B start -> B end) `0' logical COM number 0 0 0 0 * * A B A 10 0 0 0 * * B A 36 80 20 15 * * B logical COM number 0 0 0 0 * * A B A `1' 96 0 0 0 * * B A 11 50 15 20 * * B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 B 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 17 18 19 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 B 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 17 16 15 Physical COM name 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (A -> B) one area one area Normal two area (A <- B) one area one area Reversed two area - 90 - Ver.2004-06-29 NJU6854 (EN3PTL= `1') VPC (Display line number) HCT (Header COM) SHIFT[1] (COM shift A/B set) SHIFT[0] (COM shift direction) SSC1 (Scan Start COM 1) SSC2 (Scan Start COM 2) PCC1 (Line No. of partial display 1) PCC2 (Line No. of partial display 2) SSC3 (Scan Start COM 3) PCC3 (Line No. of partial display 3) logical COM number 0 0 0 0 * * `0' 10 0 0 0 * * 36 80 20 15 * * logical COM number 0 0 0 0 * * 106 13 `1' (B start-> B end -> A start -> A end) `1' 96 0 0 0 * * 11 50 15 20 * * A COMA0 COMA1 COMA2 COMA3 COMA4 COMA5 COMA6 COMA7 COMA8 COMA9 COMA10 COMA11 COMA12 COMA13 COMA14 COMA15 COMA16 COMA17 COMA18 COMA19 COMA20 COMA21 COMA22 COMA23 COMA24 COMA25 COMA26 COMA27 COMA28 COMA29 COMA30 COMA31 COMA32 COMA33 COMA34 COMA35 COMA36 COMA37 COMA38 COMA39 COMA40 COMA41 COMA42 COMA43 COMA44 COMA45 COMA46 COMA47 COMA48 COMA49 COMA50 COMA51 COMA52 COMA53 COMA54 COMA55 COMA56 COMA57 COMA58 COMA59 COMA60 COMA61 COMA62 COMA63 COMA64 COMA65 B COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 COMB8 COMB9 COMB10 COMB11 COMB12 COMB13 COMB14 COMB15 COMB16 COMB17 COMB18 COMB19 COMB20 COMB21 COMB22 COMB23 COMB24 COMB25 COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB33 COMB34 COMB35 COMB36 COMB37 COMB38 COMB39 COMB40 COMB41 COMB42 COMB43 COMB44 COMB45 COMB46 COMB47 COMB48 COMB49 COMB50 COMB51 COMB52 COMB53 COMB54 COMB55 COMB56 COMB57 COMB58 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 A 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A B A B A B A 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 A B A B A B 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 17 16 15 Physical COM name 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 REMARK (B -> A) one area one area Normal two area (B <- A) one area one area Reversed two area Ver.2004-06-29 - 91 - NJU6854 (EN3PTL= `1') VPC (Display line number) HCT (Header COM) SHIFT[1] (COM shift A/B set) SHIFT[0] (COM shift direction) SSC1 (Scan Start COM 1) SSC2 (Scan Start COM 2) PCC1 (Line No. of partial display 1) PCC2 (Line No. of partial display 2) SSC3 (Scan Start COM 3) PCC3 (Line No. of partial display 3) logical COM number 0 0 0 0 0 0 `0' 10 0 0 0 0 0 36 80 20 15 101 5 logical COM number 0 0 0 0 0 0 106 13 `0' (A start-> A end -> B start -> B end) `1' 96 0 0 0 0 0 0 11 5 15 50 20 A COMA0 COMA1 COMA2 COMA3 COMA4 COMA5 COMA6 COMA7 COMA8 COMA9 COMA10 COMA11 COMA12 COMA13 COMA14 COMA15 COMA16 COMA17 COMA18 COMA19 COMA20 COMA21 COMA22 COMA23 COMA24 COMA25 COMA26 COMA27 COMA28 COMA29 COMA30 COMA31 COMA32 COMA33 COMA34 COMA35 COMA36 COMA37 COMA38 COMA39 COMA40 COMA41 COMA42 COMA43 COMA44 COMA45 COMA46 COMA47 COMA48 COMA49 COMA50 COMA51 COMA52 COMA53 COMA54 COMA55 COMA56 COMA57 COMA58 COMA59 COMA60 COMA61 COMA62 COMA63 COMA64 COMA65 B COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 COMB8 COMB9 COMB10 COMB11 COMB12 COMB13 COMB14 COMB15 COMB16 COMB17 COMB18 COMB19 COMB20 COMB21 COMB22 COMB23 COMB24 COMB25 COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB33 COMB34 COMB35 COMB36 COMB37 COMB38 COMB39 COMB40 COMB41 COMB42 COMB43 COMB44 COMB45 COMB46 COMB47 COMB48 COMB49 COMB50 COMB51 COMB52 COMB53 COMB54 COMB55 COMB56 COMB57 COMB58 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 B 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A B A B A B A 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 B 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B A B A B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 17 18 19 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 20 Physical COM name 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REMARK (A -> B) one area one area Normal two area (A <- B) one area one area Reversed two area - 92 - Ver.2004-06-29 NJU6854 (EN3PTL= `1') VPC (Display line number) HCT (Header COM) SHIFT[1] (COM shift A/B set) SHIFT[0] (COM shift direction) SSC1 (Scan Start COM 1) SSC2 (Scan Start COM 2) PCC1 (Line No. of partial display 1) PCC2 (Line No. of partial display 2) SSC3 (Scan Start COM 3) PCC3 (Line No. of partial display 3) logical COM number 0 0 0 0 0 0 `0' 10 0 0 0 0 0 36 80 20 15 101 5 logical COM number 0 0 0 0 0 0 106 13 `1' (B start-> B end -> A start -> A end) `1' 96 0 0 0 0 0 0 11 5 15 20 10 A COMA0 COMA1 COMA2 COMA3 COMA4 COMA5 COMA6 COMA7 COMA8 COMA9 COMA10 COMA11 COMA12 COMA13 COMA14 COMA15 COMA16 COMA17 COMA18 COMA19 COMA20 COMA21 COMA22 COMA23 COMA24 COMA25 COMA26 COMA27 COMA28 COMA29 COMA30 COMA31 COMA32 COMA33 COMA34 COMA35 COMA36 COMA37 COMA38 COMA39 COMA40 COMA41 COMA42 COMA43 COMA44 COMA45 COMA46 COMA47 COMA48 COMA49 COMA50 COMA51 COMA52 COMA53 COMA54 COMA55 COMA56 COMA57 COMA58 COMA59 COMA60 COMA61 COMA62 COMA63 COMA64 COMA65 B COMB0 COMB1 COMB2 COMB3 COMB4 COMB5 COMB6 COMB7 COMB8 COMB9 COMB10 COMB11 COMB12 COMB13 COMB14 COMB15 COMB16 COMB17 COMB18 COMB19 COMB20 COMB21 COMB22 COMB23 COMB24 COMB25 COMB26 COMB27 COMB28 COMB29 COMB30 COMB31 COMB32 COMB33 COMB34 COMB35 COMB36 COMB37 COMB38 COMB39 COMB40 COMB41 COMB42 COMB43 COMB44 COMB45 COMB46 COMB47 COMB48 COMB49 COMB50 COMB51 COMB52 COMB53 COMB54 COMB55 COMB56 COMB57 COMB58 COMB59 COMB60 COMB61 COMB62 COMB63 COMB64 COMB65 A 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A B A B A B A 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 A B A B A B 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 22 21 20 Physical COM name 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 REMARK (B -> A) one area one area Normal two area (B <- A) one area one area Reversed two area Ver.2004-06-29 - 93 - NJU6854 Example of panel connection 1 (HCT=00H) Physical COM Layout Scanning Direction SHIFT[1:0] =(0,1) 00H PANEL 00H RAM Mapping X Address 83H Scanning Direction COMB[65~0] SHIFT[1:0] =(0,0) COMA[0~65] Example of panel connection 2 (HCT=0AH) Physical COM Layout Scanning Direction SHIFT[1:0] =(0,1) 00H PANEL 00H Y Address 83H RAM Mapping X Address 83H Scanning Direction COMB[65~10] SHIFT[1:0] =(0,0) COMA[10~65] Y Address 6FH 70H 83H - 94 - Ver.2004-06-29 NJU6854 (15) TYPICAL INSTRUCTION SEQUENCES (1) Initialization (internal power supply) VDD, VEE - VSS RESb="L" Note 1 ) If VEE is different from VDD, input VDD first Note 2) Waiting until VDD and VEE stabilization Power Supply Stabilization RESb="H" Note 3) Waiting at least 10 us WAIT Bus length selection 8 or 16-bit bus length selection Display Control Duty ratio Blank line number N-line inversion Display mode Power Supply Boost level, amplifier gain for VREG Electronic volume Bias ratio VREG, VBA Power Control (CKCONT="1", DCON="1") Note 4) Waiting until VOUT stabilization WAIT Note 5) Waiting until V0 and V1~V4 stabilization Power Supply Power control (AMPON="1") WAIT End of Initialization Ver.2004-06-29 - 95 - NJU6854 (2) Initialization (external power supply) VDD ON, RESb="L" Note 1) Waiting until VDD stabilization Power supply stabilization Note 2) Waiting at least 10 us RESb="H" Note 3) Waiting until VOUT, V0~V4 stabilization VOUT, V0~V4 ON WAIT Display Control Duty ratio Blank line number N-line inversion Display mode End of Initialization (3) Data Write Initialization Display Control Initial Display Line Display data configuration / window area X address Y address Display data write Display data ON (ON/OFF="1") End of display data setting (4) Power OFF Optional condition Function Execute HALT or reset instruction (All drivers outputs VSS) Execute discharge instruction (V0 and V1~V4 capacitors discharge) Wait VEE, VDD~VSS OFF Ver.2004-06-29 - 96 - NJU6854 (5) Partial Display Optional Condition Display OFF(ON/OFF="0") Internal power supply OFF (DCON="0", AMPON="0") Note 1) Waiting until voltage booster OFF WAIT Power Supply Boost Lever, amplifier gain of VREG Electronic volume Bias ratio VREG, VBA Power control Note 2) Waiting until VOUT stabilization (DCON="1", AMPON="1") WAIT Note 3) Waiting until VOUT V0 and V1 ~V4 stabilization Display Control Duty ratio Initial display line Partial display Display ON(ON/OFF="1") Partial display ON Ver.2004-06-29 - 97 - NJU6854 ! ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITION TERMINAL RATING Supply Voltage (1) VDD VDD -0.3 to +4.0 Supply Voltage (2) VEE VEE -0.3 to +4.0 Supply Voltage (3) VOUT VOUT -0.3 to +20.0 VSS=0V Supply Voltage (4) VREG VREG -0.3 to +20.0 Ta = +25C Supply Voltage (5) V0 V0 -0.3 to +20.0 Supply Voltage (6) V1, V2, V3, V4 V1, V2, V3, V4 -0.3 to V0 + 0.3 Input Voltage VI *1 -0.3 to VDD + 0.3 Storage Temperature Tstg -45 to +125 Note 1) D0 ~ D15, CSb, RS, RDb, WRb, OSCI, RESb pins Note 2) To stabilize the LSI operation, place decoupling capacitors between VDD and VSS, VEE and VSSH. UNIT V V V V V V V C ! RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage SYMBOL VDD1 VDD2 VEE V0 VOUT VREG VREF TERMINAL VDD VEE V0 VOUT VREG VREF MIN 1.7 2.4 2.4 5 TYP MAX UNIT 3.3 V 3.3 V 3.3 V 18.0 V 18.0 V V VOUT x 0.9 3.3 V 85 NOTE *1 *2 *3 *4 *5 Operating Voltage 1.59(TBD) Operating Topr -30 Temperature Note1) Applies to the condition when the reference voltage generator is not used. Note2) Applies to the condition when the reference voltage generator is used. Note3) Applies to the condition when the voltage booster is used. Note4) The following relationship among the supply voltages must be maintained. VSSH - 98 - Ver.2004-06-29 NJU6854 ! DC CHARACTERISTICS SYM PARAMETER BOL High level input voltage VIH Low level input voltage VIL High level output voltage VOH1 Low level output voltage VOL1 High level output voltage VOH2 Low level output voltage VOL2 Input leakage current ILI Output leakage current ILO Driver ON-resistance Stand-by current Internal oscillation Frequency External oscillation Frequency Voltage converter output voltage Supply current (1) Supply current (2) Supply current (3) Supply current (4) Supply current (5) Supply current (6) VBA Operating voltage VREG Operating voltage RON1 ISTB fOSCI fOSC2 fOSC3 fOSC4 fr1 VOUT IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VBA VREG V2 V3 VD12 VD34 VD24 VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85C NOT CONDITION MIN TYP MAX UNIT E 0.8 VDD VDD V *1 0 0.2VDD V *1 IOH = -0.4mA VDD - 0.4 V *2 IOL = 0.4mA 0.4 V *2 IOH = -0.1mA VDD - 0.4 V *3 IOL = 0.1mA 0.4 V *3 *4 -10 10 VI = VSS or VDD A *5 -10 10 VI = VSS or VDD A V0 = 10V 1 2 *6 k |VON| = 0.5V 2 4 V0 = 6V *7 15 CSb=VDD, Ta=25C VDD = 3V A TBD 730 TBD VDD = 3V TBD 170 TBD kHz *8 Ta = 25C TBD 1200 TBD TBD 285 TBD Rf=15k, VDD = 3V,Ta = 25C N-time booster (N=2 to 6) RL = 500k (VOUT - VSS) VDD = 3V, 6-time booster Whole ON pattern VDD = 3V, 6-time booster Checker pattern VDD = 3V, 5-time booster Whole ON pattern VDD = 3V, 5-time booster Checker pattern VDD = 3V, 4-time booster Whole ON pattern VDD = 3V, 4-time booster Checker pattern VEE = 2.4 to 3.3V@ T=25C VEE = 2.4 to 3.3V VREF = 1.9 N-time booster (N=2 to 6) (N x VEE) x 0.95 TBD(760) TBD(1140) TBD(930) TBD(1400) TBD(520) TBD(650) TBD(360) TBD(450) 1.86 1.9 (VREF x N) (VREF x N) x 0.97 -100 -100 -30 -30 -30 0 0 0 0 0 TBD(780) TBD(980) TBD(540) TBD(680) 1.94 (VREF x N) x 1.03 +100 +100 +30 +30 +30 V V *12 *13 730 kHz V *9 *10 A *11 Output Voltage mV *14 Ver.2004-06-29 - 99 - NJU6854 Applicable Pins and Conditions *1 *2 *3 *4 *5 *6 D0-D15, CSb, RS, RDb, WRb, PS, SEL68, RESb D0-D15 LP, FLM, M CSb, RS, SEL68, RDb, WRb, PS, RESb, OSCI D0-D15 , M, FLM, LP in the high impedance SEGA0-SEGA131, SEGB0-SEGB131, SEGC0-SEGC131, COMA0-COMA65, COMB0-COMB65 Defines the resistance between the COM/SEG terminals and the power supply terminals (V0, V1, V2, V3 and V4) at the condition of 0.5V deference and 1/9 LCD bias ratio. VDD The oscillator is halted, CSb="1" (disabled), No-load on the COM/SEG drivers fOSCI - Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 0, 0). fOSC2 - Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 0, 1). fOSC3 - Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (1, 0, 0). fOSC4 - Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (1, 0, 1). fr1 - Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 1, 0). VOUT - N x boosting (N=2~6), applicable under internal oscillator circuit and internal power circuit are ON state. - VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/5 to 1/12 LCD bias, duty is 1/132 , No loads on COM/SEG drivers. - RL=500K between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON="1", AMPON="1" VDD - Applies to the condition using the internal oscillator and internal power circuits, no access between the LSI and MPU. EVR value is `1,1,1,1,1,1,1'. Driving patterns are `all pixels turned-on' or `checkerboard' display in grayscale mode. No load are connected on the COM/SEG drivers. - VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON="1", AMPON="1", NLIN="0", 1/132 Duty cycle, Ta=25C VBA VEE=2.4V to 3.3V , Ta=25C VREG - VEE=2.4V to 3.3V, VREF=1.9(external)V, VOUT=18V, bias ratio is from 1/5 to 1/12, 1/132 duty cycle, EVR=(1,1,1,1,1,1,1), Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 6. CA1=CA2=1.0uF, CA3=0.1uF, DCON="0", AMPON="1", NLIN="0" V0, V1, V2, V3, V4 - VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-load on the COM/SEG drivers, voltage booster N=5. CA1=CA2=1.0uF, CA3=0.1uF, DCON="0", AMPON="1" 1 2 V2 V3 3 V4 4 VSS V0 V1 VD12 = 1 - 2 VD34 = 3 - 4 VD24 = 2 - 4 *7 *8 *9 *10 *11 *12 *13 *14 (VD24 is applied to the condition that VD12 and VD34 are out of specifications.) - 100 - Ver.2004-06-29 NJU6854 ! AC CHARACTERISTICS (1) Write operation (80-type MPU) tAS8 CSb RS tAH8 WRb tWRLW8 tWRHW8 tDS8 tDH8 D0 to D15 tCYC8 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 240 110 110 60 15 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns ns ns WRb D0 to D15 (VDD=1.7 to 2.5V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 300 95 95 80 20 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS WRb D0 to D15 Note) Each timing is specified based on 20% and 80% of VDD. Ver.2004-06-29 - 101 - NJU6854 (2) Read operation (80-type MPU) tAS8 CSb RS tAH8 RDb tWRLR8 tWRHR8 tRDH8 D0 to D15 tRDD8 tCYC8 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns 90 0 ns ns RDb PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 TRDD8 TRDH8 CONDITION MIN. 0 0 260 120 120 CL=15pF D0 to D15 (VDD=1.7 to 2.5V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CL=15pF CONDITION MIN. 0 0 360 170 170 150 0 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS RDb D0 to D15 Note) Each timing is specified based on 20% and 80% of VDD. - 102 - Ver.2004-06-29 NJU6854 (3) Write operation (68-type MPU) tAS6 CSb RS R/W (WRb) tAH6 E (RDb) tEHW6 tDS6 tDH6 tELW6 D0 to D15 tCYC6 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 240 110 110 70 15 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns ns ns E D0 to D15 (VDD=1.7 to 2.5V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 300 95 95 80 20 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS E D0 to D15 Note) Each timing is specified based on 20% and 80% of VDD. Ver.2004-06-29 - 103 - NJU6854 (4) Read operation (68-type MPU) tAS6 CSb RS tAH6 R/W (WRb) tELR6 E (RDb) tRDH6 tEHR6 D0 to D15 tRDD6 tCYC6 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns 100 0 ns ns E PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 CONDITION MIN. 0 0 260 120 120 CL=15pF D0 to D15 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 CONDITION MIN. 0 0 360 170 170 (VDD=1.7 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns 150 ns ns E CL=15pF 0 D0 to D15 Note) Each timing is specified based on 20% and 80% of VDD. - 104 - Ver.2004-06-29 NJU6854 (5) Serial interface CSb tCSS tCSH RS tASS SCL tSHW tCYCS tSLW tAHS tDSS tDHS SDA (VDD=2.5 to 3.3V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. TBD(75) TBD(33) TBD(33) TBD(33) TBD(33) TBD(33) TBD(33) TBD(33) TBD(33) MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb (VDD=1.7 to 2.5V, Ta=-30 to +85C) PARAMETER SYMBOL CONDITION tCYCS Serial clock cycle SCL "H" level pulse width tSHW SCL "L" level pulse width tSLW Address setup time tASS Address hold time tAHS Data setup time tDSS Data hold time tDHS CSb - SCL time tCSS tCSH CSb hold time Note) Each timing is specified based on 20% and 80% of VDD. MIN. TBD(120) TBD(55) TBD(55) TBD(55) TBD(55) TBD(55) TBD(55) TBD(55) TBD(55) MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb Ver.2004-06-29 - 105 - NJU6854 (6) Display control timing OSCI tDLP LP tDFLM tDFLM FLM tM M Output timing PARAMETER FLM delay time FR delay time CL delay time SYMBOL tDFLM tFR tDCL CONDITION CL=15pF MIN. 0 0 0 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. 500 500 200 UNIT ns ns ns TERMINAL FLM FR CL Output timing PARAMETER SYMBOL CONDITION FLM delay time tDFLM CL=15pF FR delay time tFR CL delay time tDCL Note) Each timing is specified based on 20% and 80% of VDD. MIN. 0 0 0 (VDD=1.7 to 2.5V, Ta=-30 to +85C) MAX. 1000 1000 200 UNIT ns ns ns TERMINAL FLM FR CL - 106 - Ver.2004-06-29 NJU6854 (7) Reset input timing RESb tRW tR Internal circuit status During reset End of reset PARAMETER Reset time RESb "L" level pulse width SYMBOL tR tRW CONDITION MIN. (VDD=2.4 to 3.3V, Ta=-30 to +85C) UNIT MAX. Terminal 1.0 s s RESb 10.0 PARAMETER Reset time SYMBOL tR CONDITION MIN. MAX. 1.5 (VDD=1.7 to 2.4V, Ta=-30 to +85C) UNIT Terminal s s RESb RESb "L" level pulse width tRW Note) Each timing is specified based on 20% and 80% of VDD. 10.0 Ver.2004-06-29 - 107 - NJU6854 ! INPUT/OUTPUT BLOCK DIAGRAM PARAMETER Basic delay time of gate SYMBOL Ta=+25C, VSS=0V, VDD=3.0V MIN TYP 10 MAX UNIT ns I/O circuit types (a) Input Circuit VDD Input Input signal Applicable Pins : CSb, RS RDb, WRb, SEL68, P/S, RESb, TEST, OSCI (b) Output Circuit VDD output output signal Applicable Pins : FLM, LP, M, OSCO - 108 - Ver.2004-06-29 NJU6854 (c) Input/Output Circuit VDD input/ output Input signal input control signal VDD output control signal output signal Applicable Pins : D0 ~ D15, (d) LCD Drive Circuit for Graphic Display VLCD VLCD output control signal 1 output output control signal 3 V3/V4 output control signal 4 V1/V2 output control signal 2 Applicable Pins : SEGA0 to SEGA131 SEGB0 to SEGB131 SEGC0 to SEGC131 COMA0 to COMA65 COMB0 to COMB65 Ver.2004-06-29 - 109 - NJU6854 ! MPU Connections 80-type MPU interface 1.7 V ~ 3.3 V VCC A0 A1~A7 7 IORQ D0~D7 RDb WRb RESb reset input decoder 8 RS CSb D0~D7 RDb WRb RESb VDD 80 series GND VSS 68-type MPU interface 1.7 V ~ 3.3 V VCC A0 A1~A15 15 decoder VMA RS CSb ~ D0 ~D7 RDb(E) VDD 68 series D0 ~D7 E WRB WRb RESB RESb 8 WRb(R/W) RESb reset input VSS GND Serial interface 1.7 V ~ 3.3 V VCC A0 A1~A7 7 decoder RS CSB CSb VDD (CPU) PORT1 PORT2 GND RESb RESB reset input SDA SCL RESB RESb VSS NJU6854 NJU6854 NJU6854 - 110 - Ver.2004-06-29 NJU6854 Memo [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2004-06-29 - 111 - |
Price & Availability of NJU6854
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |